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[79.14.29.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e412cc164sm25324882f8f.7.2026.10.28.00.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 00:44:44 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Brian Masney , Jerome Brunet , Stephen Boyd , Tero Kristo , linux-clk@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v3 3/3] clk: ti: dpll: apply the spread spectrum configuration right away Date: Wed, 28 Oct 2026 08:44:09 +0100 Message-ID: <20261028074436.1958132-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028074436.1958132-1-dario.binacchi@amarulasolutions.com> References: <20261028074436.1958132-1-dario.binacchi@amarulasolutions.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The spread spectrum clocking (SSC) registers are only programmed by set_rate(), which the clock core skips when the requested rate is already the current one, e.g. when the bootloader has set it up. As a result, the SSC configuration is not applied, as it was with the vendor specific properties. Apply it from set_spread_spectrum() instead, reprogramming the DPLL at its current rate. Signed-off-by: Dario Binacchi --- Changes in v3: - Skip reprogramming only if the configuration is already applied to the hardware Changes in v2: - Check the DPLL lock state instead of its parent, as the reference and bypass clocks can be the same clock drivers/clk/ti/dpll3xxx.c | 49 ++++++++++++++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 6 deletions(-) diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index 634fe0a1f9fd..d32d81a27bfe 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -690,17 +690,22 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, * @hw: pointer to the clock to set the spread spectrum configuration for * @ss_conf: spread spectrum configuration * - * Stores the spread spectrum clocking (SSC) configuration of the DPLL. The - * configuration is programmed along with the DPLL multiplier and divider - * at the next rate change. The hardware supports center-spread and - * down-spread only. Returns 0 on success, or a negative error value on - * failure. + * Stores the spread spectrum clocking (SSC) configuration of the DPLL and, + * if the DPLL is locked, reprograms it at its current rate to apply it. + * Otherwise the configuration is applied at the next rate change. The + * hardware supports center-spread and down-spread only. Returns 0 on + * success, negative error value otherwise. */ int omap3_noncore_dpll_set_spread_spectrum(struct clk_hw *hw, const struct clk_spread_spectrum *ss_conf) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct dpll_data *dd = clk->dpll_data; + struct clk_spread_spectrum old_conf; + struct clk_rate_request req; + unsigned long rate; + int ret; + u32 ctrl; if (!dd || !dd->ssc_enable_mask) return -EOPNOTSUPP; @@ -718,9 +723,41 @@ int omap3_noncore_dpll_set_spread_spectrum(struct clk_hw *hw, return -EINVAL; } + ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); + + /* Already applied */ + if (!memcmp(ss_conf, &dd->ssc_conf, sizeof(*ss_conf)) && + !!(ctrl & dd->ssc_enable_mask) == (ss_conf->method != CLK_SPREAD_NO)) + return 0; + + old_conf = dd->ssc_conf; dd->ssc_conf = *ss_conf; - return 0; + /* Disabling SSC does not need to reprogram the DPLL */ + if (ss_conf->method == CLK_SPREAD_NO) { + omap3_noncore_dpll_ssc_program(clk); + return 0; + } + + /* Not locked: SSC is programmed along with the next rate change */ + if (((ctrl & dd->enable_mask) >> __ffs(dd->enable_mask)) != DPLL_LOCKED) + return 0; + + rate = clk_hw_get_rate(hw); + clk_hw_init_rate_request(hw, &req, rate); + ret = omap2_dpll_determine_rate(hw, &req); + if (!ret && req.rate != rate) + ret = -EINVAL; + if (!ret) + ret = omap3_noncore_dpll_set_rate(hw, rate, + clk_hw_get_rate(dd->clk_ref)); + if (ret) { + pr_warn("clock: %s: rate %lu can't be kept with SSC enabled\n", + clk_hw_get_name(hw), rate); + dd->ssc_conf = old_conf; + } + + return ret; } /** -- 2.43.0