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Wed, 28 Oct 2026 01:49:14 -0700 From: Johnny Liu To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , "Prashant Gaikwad" , Stephen Boyd , Brian Masney , Jerome Brunet , "Douglas Anderson" , Aniruddha Rao , , , , CC: Johnny Liu Subject: [PATCH 0/5] Add Tegra238 BPMP support and fix stale EMC clock rate Date: Wed, 28 Oct 2026 08:48:55 +0000 Message-ID: <20261028084900.1047287-1-johnliu@nvidia.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH4PEPF0000B60E:EE_|DS7PR12MB8230:EE_ X-MS-Office365-Filtering-Correlation-Id: f4354b01-3551-46be-1d45-08df34d060e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|7416014|376014|82310400026|36860700016|921020|11063799006|56012099006|261022105027099003|261009223027099003|261026121527099003|261026140227099003|261021121427099003|261021123027099003|10067099003|18002099003; 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This series makes the EMC clock rate uncached on Tegra234, Tegra238 and Tegra264, and adds the pieces needed to identify the EMC clock on each of these chips. The EMC clock ID differs per chip (TEGRA234_CLK_EMC=31, TEGRA238_CLK_EMC=43, TEGRA264_CLK_EMC=290), while the "nvidia,tegra186-bpmp" fallback compatible and the tegra186_soc data are shared across several chips. To avoid detecting the chip at runtime, the EMC clock ID is carried in per-SoC BPMP data selected by the device tree compatible. Patch 1 adds the Tegra238 clock ID header, following the format and naming used for Tegra264. Patch 2 adds the "nvidia,tegra238-bpmp" compatible to the binding. Patch 3 adds dedicated SoC data for Tegra234, Tegra238 and Tegra264, selected by their specific compatibles, and builds the BPMP driver for CONFIG_ARCH_TEGRA_238_SOC. Patch 4 adds an emc_clk_id field to struct tegra_bpmp_soc and sets it using the TEGRA*_CLK_EMC clock ID macros. Patch 5 then sets CLK_GET_RATE_NOCACHE on the clock matching that ID. The series touches both the clock and the firmware code. Patch 5 depends on patch 4, which in turn depends on patch 1, so I would suggest taking the whole series through the Tegra tree with an Acked-by from the clock maintainers. Johnny Liu (5): dt-bindings: clock: Add Tegra238 BPMP clock IDs dt-bindings: firmware: tegra186-bpmp: Add Tegra238 compatible firmware: tegra: bpmp: Add Tegra238 support firmware: tegra: bpmp: Add per-SoC EMC clock ID clk: tegra: bpmp: Do not cache the EMC clock rate .../firmware/nvidia,tegra186-bpmp.yaml | 1 + drivers/clk/tegra/clk-bpmp.c | 3 + drivers/firmware/tegra/Makefile | 1 + drivers/firmware/tegra/bpmp.c | 61 ++-- include/dt-bindings/clock/nvidia,tegra238.h | 279 ++++++++++++++++++ include/soc/tegra/bpmp.h | 1 + 6 files changed, 329 insertions(+), 17 deletions(-) create mode 100644 include/dt-bindings/clock/nvidia,tegra238.h -- 2.43.0