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This series has been tested on the JHB100 SoC. Changes since v1: - Add a new patch 1 Patch 2: - Remove DDR instruction support; currently only supports 1S-nD-nD. - Add dw_spi_supports_enh_ddr_op() to reject invalid DTR operations. - Use the new DW_SPI_CAP_DDR flag to indicate DTR support. - Use addr_data_ddr naming instead of spi_ddr. Patch 3: - Rework spi_nor_spimem_setup_op() so the command extension, 2-byte opcode and SNOR_F_SWAP16 handling apply only to the 8D-8D-8D DTR protocol. For 1S-xD-xD protocols the opcode remains a single byte sent in STR, and only the address, dummy and data phases are switched to DTR. Patch 4: - Add Miquel's Reviewed-by tag. Patch 5: - Add Miquel's Reviewed-by tag. - Update commit message. v1: https://lore.kernel.org/all/20261022102614.75696-1-changhuang.liang@starfivetech.com/ Changhuang Liang (5): spi: dw: Detect DDR support in enhanced SPI mode spi: dw: Add DDR (Dual Data-Rate) support for enhanced SPI mode mtd: spi-nor: Support mixed 1S-xD-xD DTR protocols in spi_nor_spimem_setup_op() mtd: spi-nor: debugfs: Correct DTR protocol names for 1S-xD-xD modes mtd: spi-nor: macronix: Add 1-4-4 DTR read support for MX66L1G45G drivers/mtd/spi-nor/core.c | 23 ++++---- drivers/mtd/spi-nor/debugfs.c | 8 +-- drivers/mtd/spi-nor/macronix.c | 28 +++++++++- drivers/spi/spi-dw-core.c | 96 ++++++++++++++++++++++++++++++---- drivers/spi/spi-dw.h | 6 +++ 5 files changed, 133 insertions(+), 28 deletions(-) -- 2.25.1