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Wed, 28 Oct 2026 06:59:19 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.42.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a94f05f168sm37077165e9.4.2026.10.28.06.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 06:59:18 -0700 (PDT) From: Dario Binacchi To: Alexandre Torgue , Stephen Boyd Cc: Marek Vasut , Gabriel Fernandez , michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Yannick Fertre , Raphael Gallais-Pou , Dario Binacchi , Brian Masney , Conor Dooley , Fabrice Gasnier , Jerome Brunet , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 0/4] Select the STM32MP25 LTDC pixel clock source for the RGB output Date: Wed, 28 Oct 2026 14:59:04 +0100 Message-ID: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On STM32MP25 the LTDC pixel clock is selected in the SYSCFG DISPLAYCLKCR register among the DSI byte lane clock, the LVDS PHY pixel clock (reset value) and the LTDC kernel clock. The SYSCFG node is already described as provider of this clock, which the LTDC references as "ref" clock, but no driver registers it, so the RGB (DPI) output can't work. This series adds a driver for this mux, probed as an auxiliary device of the STM32MP2 SYSCFG driver, and selects the pixel clock source on the Engicam MicroGEA-STM32MP257D-RMM display overlays. Patch 1 is an independent fix for the RGB display overlay. Tested on the Engicam MicroGEA-STM32MP257D-RMM board with both the RGB (Rocktech RK050HR345-CT106A) and the LVDS (Ampire AM-1280800W8TZQW-T00H) displays. I am sending it as RFC since I am not sure about: - the mux parents are referenced by their global names. Should they rather be described by clocks/clock-names in the SYSCFG binding? Moreover, no driver registers "txbyteclk" yet. - the pixel clock source is selected in the board devicetree by assigned-clock-parents. Should the LTDC driver rather select it according to its output (RGB, LVDS or DSI)? Dario Binacchi (4): arm64: dts: st: fix the Engicam RMM RGB display pixel clock clk: stm32: add STM32MP25 SYSCFG clock driver soc: st: stm32mp2-syscfg: register the STM32MP25 clock device arm64: dts: st: select the Engicam RMM display pixel clock source ...gea-rmm-overlay-am-1280800w8tzqw-t00h.dtso | 3 + ...icrogea-rmm-overlay-rk050hr345-ct106a.dtso | 5 + drivers/clk/stm32/Kconfig | 12 ++ drivers/clk/stm32/Makefile | 1 + drivers/clk/stm32/clk-stm32mp25-syscfg.c | 111 ++++++++++++++++++ drivers/soc/st/Kconfig | 1 + drivers/soc/st/stm32mp2-syscfg.c | 28 ++++- 7 files changed, 159 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/stm32/clk-stm32mp25-syscfg.c --- base-commit: 65ba8f34ec886ec72b2c07ddc8cf3d815c32869d branch: stm32mp25-ltdc-pixclk -- 2.43.0