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Wed, 28 Oct 2026 06:59:26 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.42.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a94f05f168sm37077165e9.4.2026.10.28.06.59.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 06:59:26 -0700 (PDT) From: Dario Binacchi To: Alexandre Torgue , Stephen Boyd Cc: Marek Vasut , Gabriel Fernandez , michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Yannick Fertre , Raphael Gallais-Pou , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 4/4] arm64: dts: st: select the Engicam RMM display pixel clock source Date: Wed, 28 Oct 2026 14:59:08 +0100 Message-ID: <20261028135915.2665857-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> References: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On STM32MP255/257 the LTDC pixel clock is selected by the SYSCFG pixel clock mux, whose reset value is the LVDS PHY pixel clock. With the RGB panel the LTDC is then clocked by the unused LVDS PHY, and every commit times out: [CRTC:42:crtc-0] vblank wait timed out [drm] *ERROR* flip_done timed out Select the LTDC kernel clock as pixel clock source in the RGB panel overlay and, for consistency, without relying on the reset value, the LVDS PHY pixel clock in the LVDS panel overlay. Signed-off-by: Dario Binacchi --- ...57d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso | 3 +++ ...2mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso | 2 ++ 2 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso index 7655c1bf56b1..b44e1d3ddb1b 100644 --- a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso +++ b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso @@ -32,6 +32,9 @@ &framebuffer { }; <dc { + /* LVDS output: the pixel clock is the LVDS PHY one */ + assigned-clocks = <&syscfg>; + assigned-clock-parents = <&lvds>; status = "okay"; port { diff --git a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso index 7be955be58ed..7855086c33c7 100644 --- a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso +++ b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso @@ -38,6 +38,8 @@ touchscreen@38 { <dc { /* RGB output: the pixel clock is the LTDC kernel clock */ clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>; + assigned-clocks = <&syscfg>; + assigned-clock-parents = <&rcc CK_KER_LTDC>; pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; pinctrl-1 = <<dc_sleep_pins_a>; -- 2.43.0