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Wed, 28 Oct 2026 16:55:37 +0000 (GMT) Received: from pps.filterd (apblrppmta01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.11/8.18.1.11) with ESMTP id 69SGtYoC1881524; Wed, 28 Oct 2026 16:55:34 GMT Received: from hu-devc-blr-u24-a.qualcomm.com (hu-anuppate-blr.qualcomm.com [10.131.36.165]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 69SGtYPS1881493 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Wed, 28 Oct 2026 16:55:34 +0000 (GMT) Received: by hu-devc-blr-u24-a.qualcomm.com (Postfix, from userid 486687) id 2F70A24AD0; Wed, 28 Oct 2026 22:25:33 +0530 (+0530) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Himanshu Chauhan , Conor Dooley , Atish Patra , Anup Patel Cc: Zhanpeng Zhang , Yunhui Cui , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Will Deacon , Thomas Gleixner , Jonathan Corbet , Randy Dunlap , Shuah Khan , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: [PATCH v11 3/9] riscv: sse: mask events during shutdown and kexec Date: Wed, 28 Oct 2026 22:25:25 +0530 Message-ID: <20261028165531.940336-4-anup.patel@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028165531.940336-1-anup.patel@oss.qualcomm.com> References: <20261028165531.940336-1-anup.patel@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Reinject: loops=2 maxloops=12 X-QCInternal: smtphost X-QCInternal: smtphost X-Authority-Analysis: v=2.4 cv=frhJ914f c=1 sm=1 tr=0 ts=6ae2290a cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=660iZSQnnn4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=968KyxNXAAAA:8 a=EUspDBNiAAAA:8 a=A1KMLtFEN3waitHq4QkA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI4MDA2NyBTYWx0ZWRfX8W1yP1aNhOTw 5vY04HBexRxbAs2pxDAsGONDv+6/zg9+xf2kRRNpuOYjh/Nujzb5HzfGJg3AII25011B+QcbSw8 aL1VEJC462WlVMRhNaQXUM3MoTXOxuU= X-Proofpoint-GUID: UriRaUMSKL_CAWC5xzAysYLaMIX53FvR X-Proofpoint-ORIG-GUID: UriRaUMSKL_CAWC5xzAysYLaMIX53FvR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI4MDA2NyBTYWx0ZWRfX27TpkGqlZA0e PZCWO4xjsscw5ZtW9aUtHFgv3SBwGWGL0kvodQduJp5Tm2s2h/9SqAtaozDDiAcsR60NdVSgccU QqHSShUeIN8jbdJBnNzLEt5C7KZJGI+U69lHrmRg+OQVE7MrSXy7oNuC6jxMbzo0kSG5SIxc52z ViR//oEm2j5fCerWutgUBph3sYhXZFXaiRLMsqkB8HGyIrUqPwaxisfO7mFeZQ67Kbc7poR8pQE QLSRlKFFguUJkqph5lYHAKFxaXeIUHmF8I+r+AEW4I+92xyemtqojTYPkgch8CjyuiiSq98VhIc J7CsTN94KOFgpnBfFLAg8hGIw+PsTzMt1LwBklslhkyvJ6uoii1P0VDH4XZkDKD63hY6Hifn2zb BHmcZeoq7GVt+RoYflnJUq1mcT9FDeC6FUIJ+MeAXGGkAdUPPcziZSwt6cVtl21rgOfZzn0l8Jk 8VDnnEGchitaNfUlqqw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-28_05,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1011 suspectscore=0 adultscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610280067 From: Zhanpeng Zhang SSE delivery is independent of normal S-mode interrupts. Firmware may also retain an event registration until Linux explicitly unregisters it. A hart must therefore stop accepting SSE events before Linux stops servicing the registered handler. Mask SSE on the local hart before panic stop, CPU stop, restart, poweroff, and crash shutdown paths. This prevents firmware from entering Linux-owned handler state after the corresponding CPU or kernel context is no longer valid. A crash kernel cannot identify or take ownership of registrations inherited from the crashed kernel. Reject a later normal kexec while such SSE state may still exist, rather than transferring unknown firmware state to another kernel. Signed-off-by: Zhanpeng Zhang Reviewed-by: Himanshu Chauhan --- arch/riscv/kernel/machine_kexec.c | 11 +++++++++++ arch/riscv/kernel/reset.c | 18 ++++++++++++++++++ arch/riscv/kernel/smp.c | 17 +++++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c index 738df176ff6f..24e7affae70b 100644 --- a/arch/riscv/kernel/machine_kexec.c +++ b/arch/riscv/kernel/machine_kexec.c @@ -14,10 +14,13 @@ #include /* For set_memory_x() */ #include /* For unreachable() */ #include /* For cpu_down() */ +#include #include #include #include +#include + /* * machine_kexec_prepare - Initialize kexec * @@ -36,6 +39,13 @@ machine_kexec_prepare(struct kimage *image) unsigned int control_code_buffer_sz = 0; int i = 0; + /* A crash kernel cannot tear down registrations inherited from firmware. */ + if (is_kdump_kernel() && image->type != KEXEC_TYPE_CRASH && + riscv_sse_available()) { + pr_err("Normal kexec from a crash kernel is unsupported with SSE\n"); + return -EOPNOTSUPP; + } + /* Find the Flattened Device Tree and save its physical address */ for (i = 0; i < image->nr_segments; i++) { if (image->segment[i].memsz <= sizeof(fdt)) @@ -127,6 +137,7 @@ void machine_crash_shutdown(struct pt_regs *regs) { local_irq_disable(); + riscv_sse_mask_current_hart(); /* shutdown non-crashing cpus */ crash_smp_send_stop(); diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c index 14eb08a6db85..fdab37e7ae52 100644 --- a/arch/riscv/kernel/reset.c +++ b/arch/riscv/kernel/reset.c @@ -6,6 +6,20 @@ #include #include #include +#include + +#include + +#ifndef CONFIG_SMP +void __noreturn panic_smp_self_stop(void) +{ + riscv_sse_mask_current_hart(); + local_irq_disable(); + + for (;;) + cpu_relax(); +} +#endif static void __noreturn default_power_off(void) { @@ -18,6 +32,8 @@ EXPORT_SYMBOL(pm_power_off); void machine_restart(char *cmd) { + riscv_sse_mask_current_hart(); + /* * UpdateCapsule() depends on the system being reset via ResetSystem(). */ @@ -30,12 +46,14 @@ void machine_restart(char *cmd) void machine_halt(void) { + riscv_sse_mask_current_hart(); do_kernel_power_off(); default_power_off(); } void machine_power_off(void) { + riscv_sse_mask_current_hart(); do_kernel_power_off(); default_power_off(); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index eddbc3ad06c9..9ad38df48271 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -22,10 +22,13 @@ #include #include #include +#include #include #include #include +#include +#include enum ipi_message_type { IPI_RESCHEDULE, @@ -78,8 +81,18 @@ int riscv_hartid_to_cpuid(unsigned long hartid) return -ENOENT; } +void __noreturn panic_smp_self_stop(void) +{ + riscv_sse_mask_current_hart(); + local_irq_disable(); + + for (;;) + cpu_relax(); +} + static void ipi_stop(void) { + riscv_sse_mask_current_hart(); set_cpu_online(smp_processor_id(), false); while (1) wait_for_interrupt(); @@ -90,6 +103,7 @@ static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0); static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) { + riscv_sse_mask_current_hart(); crash_save_cpu(regs, cpu); atomic_dec(&waiting_for_crash_ipi); @@ -253,6 +267,8 @@ void smp_send_stop(void) { unsigned long timeout; + riscv_sse_mask_current_hart(); + if (num_online_cpus() > 1) { cpumask_t mask; @@ -300,6 +316,7 @@ void crash_smp_send_stop(void) return; cpus_stopped = 1; + riscv_sse_mask_current_hart(); /* * If this cpu is the only one alive at this point in time, online or -- 2.43.0