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From: Anup Patel <anup.patel@oss.qualcomm.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <pjw@kernel.org>, Alexandre Ghiti <alex@ghiti.fr>,
	Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com>,
	Conor Dooley <conor@kernel.org>,
	Atish Patra <atish.patra@linux.dev>,
	Anup Patel <anup@brainfault.org>
Cc: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>,
	Yunhui Cui <cuiyunhui@bytedance.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	James Clark <james.clark@linaro.org>,
	Will Deacon <will@kernel.org>, Thomas Gleixner <tglx@kernel.org>,
	Jonathan Corbet <corbet@lwn.net>,
	Randy Dunlap <rdunlap@infradead.org>,
	Shuah Khan <shuah@kernel.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: [PATCH v11 5/9] riscv: mm: avoid enabling interrupts for nofault page faults
Date: Wed, 28 Oct 2026 22:25:27 +0530	[thread overview]
Message-ID: <20261028165531.940336-6-anup.patel@oss.qualcomm.com> (raw)
In-Reply-To: <20261028165531.940336-1-anup.patel@oss.qualcomm.com>

From: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>

RISC-V enables interrupts in handle_page_fault() before checking whether
the fault occurred with fault handling disabled. A nofault access from an
atomic context can therefore run tracepoints and open an interrupt window
before reaching the exception-table fixup.

Handle an exception-table entry before entering the generic fault path when
fault handling is disabled. Also keep interrupts disabled until such a
fault has been resolved.

This makes RISC-V consistent with the expectation that an in-atomic
nofault access does not enter the normal fault-handling path. It also
removes one source of re-entry when perf sampling is delivered through an
SBI Supervisor Software Event (SSE).

Signed-off-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
---
 arch/riscv/mm/fault.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
index 04ed6f8acae4..520495420462 100644
--- a/arch/riscv/mm/fault.c
+++ b/arch/riscv/mm/fault.c
@@ -294,6 +294,13 @@ void handle_page_fault(struct pt_regs *regs)
 	if (kprobe_page_fault(regs, cause))
 		return;
 
+	/*
+	 * Nofault accesses must be resolved through the exception table before
+	 * entering the generic fault path or enabling interrupts.
+	 */
+	if (unlikely(faulthandler_disabled()) && fixup_exception(regs))
+		return;
+
 	if (user_mode(regs))
 		trace_page_fault_user(addr, regs, cause);
 	else
@@ -314,8 +321,8 @@ void handle_page_fault(struct pt_regs *regs)
 		return;
 	}
 
-	/* Enable interrupts if they were enabled in the parent context. */
-	if (!regs_irqs_disabled(regs))
+	/* Do not open an interrupt window before a nofault fixup completes. */
+	if (!regs_irqs_disabled(regs) && !faulthandler_disabled())
 		local_irq_enable();
 
 	/*
-- 
2.43.0


  parent reply	other threads:[~2026-10-28 16:56 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-28 16:55 [PATCH v11 0/9] riscv: add SBI Supervisor Software Events support Anup Patel
2026-10-28 16:55 ` [PATCH v11 1/9] riscv: add SBI SSE extension definitions Anup Patel
2026-10-28 16:55 ` [PATCH v11 2/9] riscv: add support for SBI Supervisor Software Events extension Anup Patel
2026-10-28 16:55 ` [PATCH v11 3/9] riscv: sse: mask events during shutdown and kexec Anup Patel
2026-10-28 16:55 ` [PATCH v11 4/9] drivers: firmware: add riscv SSE support Anup Patel
2026-10-28 16:55 ` Anup Patel [this message]
2026-10-28 16:55 ` [PATCH v11 6/9] perf: RISC-V: support callchains with SSE delivery Anup Patel
2026-10-28 16:55 ` [PATCH v11 7/9] perf: RISC-V: add support for SSE event Anup Patel
2026-10-28 16:55 ` [PATCH v11 8/9] selftests/riscv: add SSE test module Anup Patel
2026-10-28 16:55 ` [PATCH v11 9/9] selftests/riscv: add perf user-stack SSE copy regression test Anup Patel

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