From: Bjorn Helgaas <helgaas@kernel.org>
To: mhklinux@outlook.com
Cc: haiyangz@microsoft.com, wei.liu@kernel.org, decui@microsoft.com,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
robh@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-hyperv@vger.kernel.org
Subject: Re: [PATCH v3 1/1] PCI: hv: Spread load across CPUs when selecting effective affinity CPU
Date: Wed, 28 Oct 2026 12:13:48 -0500 [thread overview]
Message-ID: <20261028171348.GA560291@bhelgaas> (raw)
In-Reply-To: <20261028155559.138833-1-mhklinux@outlook.com>
On Wed, Oct 28, 2026 at 08:55:59AM -0700, Michael Kelley wrote:
> In a system with multiple devices with the same configuration (such as
> NVMe controllers), the affinity masks are the same for all such devices.
> Linux typicaly must select a single CPU from each mask to be the effective
s/typicaly/typically/
> @@ -881,25 +1016,48 @@ static int hv_pci_vec_irq_domain_alloc(struct irq_domain *domain,
> }
>
> /*
> - * Pick the first cpu as the irq affinity that can be temporarily used for
> + * Pick the first CPU as the irq affinity that can be temporarily used for
s/irq/IRQ/ if you want to follow the majority usage in this file, also
below
> * composing MSI from the hypervisor. GIC will eventually set the right
> * affinity for the irq and the 'unmask' will retarget the interrupt to that
> - * cpu.
> + * CPU.
next prev parent reply other threads:[~2026-10-28 17:13 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-28 15:55 Michael Kelley
2026-10-28 17:13 ` Bjorn Helgaas [this message]
2026-10-28 18:49 ` Michael Kelley
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