From: "Enrique Hernández Bello" <ehbello@gmail.com>
To: iav@iav.lv
Cc: shawn.lin@rock-chips.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org,
manivannan.sadhasivam@oss.qualcomm.com, bhelgaas@google.com,
robh@kernel.org, heiko@sntech.de, dlemoal@kernel.org,
linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] PCI: rockchip: Skip the Tpvperl wait when power is already valid
Date: Wed, 28 Oct 2026 17:31:08 +0000 [thread overview]
Message-ID: <20261028173108.3457165-1-ehbello@gmail.com> (raw)
In-Reply-To: <20261028-h64-tpvperl-ab-skip@iav.lv>
On Wed, 28 Oct 2026 05:10:00 +0000, Igor Velkov wrote:
> Since the next version keeps the full wait on resume, it no longer
> changes the resume path, so I'll skip the A/B and test that version
> on Helios64 instead: boots plus s2idle cycles, results in reply to it.
Thank you -- that coverage is worth a lot, but hold off a little, because the
shape is changing again.
Shawn Lin has asked for a DT property for the PERST# pulse rather than a
decision taken in the driver, matching rockchip,perst-inactive-ms and
rockchip,s2r-perst-inactive-ms in the vendor dwc driver, and I have agreed. So
the version to test is that one, not the probe-only patch I was about to send.
Whether the default changes or stays at PCIE_T_PVPERL_MS is still open, so I
will put the DT snippet to set on a Helios64 in the cover letter instead of
leaving it to guesswork.
next prev parent reply other threads:[~2026-10-28 17:31 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 21:15 Enrique Hernández Bello
2026-09-12 1:21 ` Shawn Lin
2026-09-12 14:14 ` Enrique Hernández Bello
2026-10-14 7:27 ` Manivannan Sadhasivam
2026-10-16 0:21 ` Igor Velkov
2026-10-28 0:55 ` Enrique Hernández Bello
2026-10-28 5:10 ` Igor Velkov
2026-10-28 17:31 ` Enrique Hernández Bello [this message]
2026-10-28 0:55 ` Enrique Hernández Bello
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