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[2.155.41.158]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4aa80285b2dsm6496175e9.13.2026.10.28.10.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 10:31:19 -0700 (PDT) From: =?UTF-8?q?Enrique=20Hern=C3=A1ndez=20Bello?= To: iav@iav.lv Cc: shawn.lin@rock-chips.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, robh@kernel.org, heiko@sntech.de, linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 0/2] PCI: rockchip-host: Retry training and hot-reset a JMB585 on RK3399 Date: Wed, 28 Oct 2026 17:31:17 +0000 Message-ID: <20261028173117.3457220-1-ehbello@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: References: <20261024-rockchip-pcie-resume-v1-0-58e54a5cf5f1@iav.lv> <4316c1da-f7ff-4fa5-a330-512800474e45@rock-chips.com> <20261026-rockchip-pcie-shawn-reply-1@iav.lv> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit You said both SErrors and synchronous external aborts occur. In my logs which of the two you get tracks the cluster the access runs on, which might be worth a look before you move the hook. Every asynchronous SError in rockchip_pcie_rd_conf landed on CPU4 or CPU5, the A72s, across six boots on two different kernels. The one time the same read aborted synchronously it was on CPU3, an A53. They also carry different ISS: 0xbf000002 for these config-read aborts, against 0xbf000000 for the unrelated runtime SErrors on this board. That is one synchronous case, so not a law, but it is cheap for you to test: pin enumeration to an A53 and see whether your aborts all become synchronous. It matters because only the synchronous form can be repaired. When it arrives as an SError the load has retired and there is no destination register left to write all-ones into, so no fixup can help. I prototyped the synchronous half in September: an exception-table entry consulted from do_sea(), with the driver substituting the all-ones the PCI core expects rather than only surviving. arm32 has had that for years -- imx6q_pcie_abort_handler() in dwc/pci-imx6.c decodes the faulting instruction and makes a read look like all-ones, under #ifdef CONFIG_ARM -- and arm64 has no equivalent path. It only ever worked for me with enumeration pinned to an A53, which is what made me look at the cluster in the first place. Not proposing anything, and not reviving that prototype. Yours if any of it is useful.