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Thu, 29 Oct 2026 08:41:59 -0500 From: Colin Huang Date: Thu, 29 Oct 2026 21:38:43 +0800 Subject: [PATCH v10 14/16] ARM: dts: aspeed: anacapa: Update EDSFF power status signals X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20261029-anacapa-devlop-phase-devicetree-v10-14-26ee3cf9d9d0@gmail.com> References: <20261029-anacapa-devlop-phase-devicetree-v10-0-26ee3cf9d9d0@gmail.com> In-Reply-To: <20261029-anacapa-devlop-phase-devicetree-v10-0-26ee3cf9d9d0@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Ryan Chen , Billy Tsai CC: , , , , , Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793281119; l=3287; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=tm5NcLUVr8BKlmTbfHzCsNbBGb237X8AOX24jRAPa0E=; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RcV5LGgqMBQ+AzlQr0PzTPRONsFmTP1qth51f+YUA6JYy+x7YCnHSwPrFRAwnEolA6mXqTGlvFzqwM5iF9Fr1ckmH/xkCeghBaSZ994Ze3fbw3Z0grvN5hbWG1slbZRroe/avClj5/ldc1xRvAOvEWKhqkufG3V+vk/GbHHOcBUKO40akCF3YA4PcX2XshUgJkjGCQo6vMOX6ZO73+3QF5FGbGSGY8PlKBpyHG5LEmcrGTAjA8Nbr1z8kBCtKfE3Xl+6nT8l9FQ/i4hdkuhgF1trjk3El7+iDToWbrlyuQK9QXoDdU5jtAMaGTVAH4YujYZCNErcqba0X03vl3pvj1rrQIKZJtA0hE/hstlIzD7kA7um8HhWVgirUq+xVnC5s5dU5vgGSVNhelFT2vx2ZXF7mxcJbwDYUKziB7TARMRGL884u9bSsoOkGqJi/k2/ X-OriginatorOrg: amdcloud.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2026 13:42:17.1171 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8f67087-e01f-40f5-75c2-08df35c2728f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: PH3PEPF00059619.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CHBPR12MB869915 From: Rex Fu The CPLD definition for the EDSFF power status signals has changed from PG to FLT. Update the corresponding SGPIO line names to match the CPLD definition. Signed-off-by: Rex Fu --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 10 +++++----- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi | 6 +++--- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 10 +++++----- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi index 3b3967b47980..698308049c38 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -162,7 +162,7 @@ &sgpiom0 { "L_PRSNT_EDSFF1_N", "", "R_PRSNT_EDSFF2_N", "", "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", + "EDSFF_BOOT_FLT", "", "", "", "P12V_PWR_CABLE_PRSNT_L_R", "FM_BMC_READY_PLD", "PRSNT_NFC_BOARD_R", "", @@ -208,10 +208,10 @@ &sgpiom0 { "PDB_ALERT_R_N", "", /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", - "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", - "R_EDSFF3_PG", "", + "L_EDSFF0_FLT", "", + "L_EDSFF1_FLT", "", + "R_EDSFF2_FLT", "", + "R_EDSFF3_FLT", "", "HPM_CPLD_HEART_BIT", "", "RBB_CPLD_HEART_BIT", "", "LBB_CPLD_HEART_BIT", "", diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi index e429f7be46db..f61cf5b3718c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi @@ -968,7 +968,7 @@ &sgpiom0 { "L_PRSNT_EDSFF1_N", "", "R_PRSNT_EDSFF2_N", "", "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", + "EDSFF_BOOT_FLT", "", "PWRGD_CHEH_CPU0_FPGA", "", "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", "", "", @@ -1013,8 +1013,8 @@ &sgpiom0 { "PDB_ALERT_R_N", "", /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", + "L_EDSFF0_FLT", "", "L_EDSFF1_FLT", "", + "R_EDSFF2_FLT", "", "R_EDSFF3_FLT", "", "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index 5c0d874fa24a..766aa26b6cea 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -370,7 +370,7 @@ &sgpiom0 { "L_PRSNT_EDSFF1_N", "", "R_PRSNT_EDSFF2_N", "", "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", + "EDSFF_BOOT_FLT", "", "", "", "", "FM_BMC_READY_PLD", "PRSNT_NFC_BOARD_R", "", @@ -416,10 +416,10 @@ &sgpiom0 { "PDB_ALERT_R_N", "", /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", - "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", - "R_EDSFF3_PG", "", + "L_EDSFF0_FLT", "", + "L_EDSFF1_FLT", "", + "R_EDSFF2_FLT", "", + "R_EDSFF3_FLT", "", "HPM_CPLD_HEART_BIT", "", "RBB_CPLD_HEART_BIT", "", "LBB_CPLD_HEART_BIT", "", -- 2.34.1