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spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpip4t1793268831tcfcd0a9e X-QQ-Originating-IP: JWcGZpaxS2VvXr8ks7Aa0kMOHfyGgrDNgxaWqapRT/I= Received: from [192.168.30.244] ( [localhost]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 29 Oct 2026 18:13:47 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 6520119527471735759 EX-QQ-RecipientCnt: 31 From: Xilin Wu Date: Thu, 29 Oct 2026 18:13:35 +0800 Subject: [PATCH v4 1/4] arm64: dts: qcom: sc8280xp: enable PCIe ECAM and 64-bit memory X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261029-q8b-dts-v4-1-e8e7438f5545@radxa.com> References: <20261029-q8b-dts-v4-0-e8e7438f5545@radxa.com> In-Reply-To: <20261029-q8b-dts-v4-0-e8e7438f5545@radxa.com> To: Bjorn Helgaas , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Bartosz Golaszewski , Linus Walleij , Abel Vesa Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Stephen Chen , Junhao Xie , dragon@radxa.com, Xilin Wu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Add 64-bit memory windows for devices with large BARs, such as discrete GPUs. Preserve the SA8540P PCIe2a and PCIe3a address maps to avoid regressions due to firmware differences. Signed-off-by: Xilin Wu --- arch/arm64/boot/dts/qcom/sa8540p.dtsi | 9 +++++++++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++++++++++---------- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index 23888029cc11..e5393a237497 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -180,6 +180,15 @@ &gpu_smmu { &pcie2a { compatible = "qcom,pcie-sa8540p"; + reg = <0x0 0x01c20000 0x0 0x3000>, + <0x0 0x3c000000 0x0 0xf1d>, + <0x0 0x3c000f20 0x0 0xa8>, + <0x0 0x3c001000 0x0 0x1000>, + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + + ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; linux,pci-domain = <0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index d17475c3e66c..0c4abf60d1d2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2161,13 +2161,14 @@ pcie4: pcie@1c00000 { <0x0 0x30000000 0x0 0xf1d>, <0x0 0x30000f20 0x0 0xa8>, <0x0 0x30001000 0x0 0x1000>, - <0x0 0x30100000 0x0 0x100000>, + <0x4 0x00000000 0x0 0x10000000>, <0x0 0x01c03000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, - <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; + <0x02000000 0x0 0x40000000 0x4 0x10000000 0x0 0x10000000>, + <0x03000000 0x4 0x20000000 0x4 0x20000000 0x0 0x20000000>; bus-range = <0x00 0xff>; dma-coherent; @@ -2273,13 +2274,14 @@ pcie3b: pcie@1c08000 { <0x0 0x32000000 0x0 0xf1d>, <0x0 0x32000f20 0x0 0xa8>, <0x0 0x32001000 0x0 0x1000>, - <0x0 0x32100000 0x0 0x100000>, + <0x4 0x40000000 0x0 0x10000000>, <0x0 0x01c0b000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, - <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; + <0x02000000 0x0 0x40000000 0x4 0x50000000 0x0 0x10000000>, + <0x03000000 0x4 0x60000000 0x4 0x60000000 0x0 0x20000000>; bus-range = <0x00 0xff>; dma-coherent; @@ -2383,13 +2385,14 @@ pcie3a: pcie@1c10000 { <0x0 0x34000000 0x0 0xf1d>, <0x0 0x34000f20 0x0 0xa8>, <0x0 0x34001000 0x0 0x1000>, - <0x0 0x34100000 0x0 0x100000>, + <0x4 0x80000000 0x0 0x10000000>, <0x0 0x01c13000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, - <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; + <0x02000000 0x0 0x40000000 0x4 0x90000000 0x0 0x10000000>, + <0x03000000 0x4 0xa0000000 0x4 0xa0000000 0x0 0x20000000>; bus-range = <0x00 0xff>; dma-coherent; @@ -2496,13 +2499,14 @@ pcie2b: pcie@1c18000 { <0x0 0x38000000 0x0 0xf1d>, <0x0 0x38000f20 0x0 0xa8>, <0x0 0x38001000 0x0 0x1000>, - <0x0 0x38100000 0x0 0x100000>, + <0x4 0xc0000000 0x0 0x10000000>, <0x0 0x01c1b000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, - <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; + <0x02000000 0x0 0x40000000 0x4 0xd0000000 0x0 0x10000000>, + <0x03000000 0x4 0xe0000000 0x4 0xe0000000 0x0 0x20000000>; bus-range = <0x00 0xff>; dma-coherent; @@ -2606,13 +2610,14 @@ pcie2a: pcie@1c20000 { <0x0 0x3c000000 0x0 0xf1d>, <0x0 0x3c000f20 0x0 0xa8>, <0x0 0x3c001000 0x0 0x1000>, - <0x0 0x3c100000 0x0 0x100000>, + <0x5 0x00000000 0x0 0x10000000>, <0x0 0x01c23000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, - <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; + <0x02000000 0x0 0x40000000 0x5 0x10000000 0x0 0x10000000>, + <0x03000000 0x5 0x20000000 0x5 0x20000000 0x0 0xe0000000>; bus-range = <0x00 0xff>; dma-coherent; -- 2.56.0