Re: [PATCH RFC 09/12] riscv: dts: bouffalolab: Add BL808 SoC

[Conor Dooley <conor@kernel.org>]

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On Thu, Oct 29, 2026 at 01:05:50AM -0400, Kwanghoon Son wrote:
> Add the BL808 D0 CPU, PLIC, CLINT and UART3. Leave UART3 disabled for
> boards to enable. UART3 connects directly to PLIC source 20; firmware
> sets up UART clocks and pins.
> 
> Signed-off-by: Kwanghoon Son <asdfkwang@gmail.com>
> ---
>  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 70 ++++++++++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..c739c77960c4578b87fcf2bc096ef7c8cda089bd
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	compatible = "bflb,bl808";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "thead,c906", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			mmu-type = "riscv,sv39";

> +			riscv,isa = "rv64imafdc";

Please drop this property, there shouldn't be any part of the stack that
needs it anymore.

Cheers,
Conor.

> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> +					       "zicsr", "zifencei", "zicntr", "zihpm";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +	};
> +
> +	xtal: clock-xtal {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +		interrupt-parent = <&plic>;
> +		dma-noncoherent;
> +
> +		uart3: serial@30002000 {
> +			compatible = "bflb,uart";
> +			reg = <0x30002000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&xtal>;
> +			clock-names = "baud";
> +			status = "disabled";
> +		};
> +
> +		plic: interrupt-controller@e0000000 {
> +			compatible = "bflb,bl808-plic", "thead,c900-plic";
> +			reg = <0xe0000000 0x04000000>;
> +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			riscv,ndev = <82>;
> +		};
> +
> +		timer@e4000000 {
> +			compatible = "bflb,bl808-clint", "thead,c900-clint";
> +			reg = <0xe4000000 0xc000>;
> +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> +		};
> +	};
> +};
> 
> -- 
> 2.47.3
> 

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