From: Dapeng Mi <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>,
Sandipan Das <sandipan.das@amd.com>,
Andrii Nakryiko <andrii@kernel.org>, Song Liu <song@kernel.org>,
Ravi Bangoria <ravi.bangoria@amd.com>,
Ananth Narayan <ananth.narayan@amd.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
bpf@vger.kernel.org, Dapeng Mi <dapeng1.mi@intel.com>,
Zide Chen <zide.chen@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Xudong Hao <xudong.hao@intel.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Sashiko <sashiko-bot@kernel.org>
Subject: [Patch v5 14/18] perf/x86/intel: Account arch-PEBS in lbr_pebs_users
Date: Thu, 29 Oct 2026 12:39:10 +0800 [thread overview]
Message-ID: <20261029043914.1395147-15-dapeng1.mi@linux.intel.com> (raw)
In-Reply-To: <20261029043914.1395147-1-dapeng1.mi@linux.intel.com>
lbr_pebs_users tracks how many PEBS events are currently using LBR.
It is updated for legacy PEBS events, but arch-PEBS events were missing
from that accounting.
Add the missing lbr_pebs_users accounting for arch-PEBS as well.
Reported-by: Sashiko <sashiko-bot@kernel.org>
Closes: https://lore.kernel.org/all/sashiko-outbox-179823@kernel.org/
Fixes: d243d0bb64af ("perf/x86/intel: Initialize architectural PEBS")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/lbr.c | 4 ++--
arch/x86/events/perf_event.h | 7 +++++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 790580f96040..2c9c9cf42e94 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -618,7 +618,7 @@ void intel_pmu_lbr_add(struct perf_event *event)
* be 'new'. Conversely, a new event can get installed through the
* context switch path for the first time.
*/
- if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0)
+ if (intel_pmu_has_pebs_lbr(event->pmu) && event->attr.precise_ip > 0)
cpuc->lbr_pebs_users++;
perf_sched_cb_inc(event->pmu);
if (!cpuc->lbr_users++ && !event->total_time_running)
@@ -689,7 +689,7 @@ void intel_pmu_lbr_del(struct perf_event *event)
if (event->hw.flags & PERF_X86_EVENT_LBR_SELECT)
cpuc->lbr_select = 0;
- if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0)
+ if (intel_pmu_has_pebs_lbr(event->pmu) && event->attr.precise_ip > 0)
cpuc->lbr_pebs_users--;
cpuc->lbr_users--;
WARN_ON_ONCE(cpuc->lbr_users < 0);
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 2b942a445038..82e0c20e435d 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -2085,6 +2085,13 @@ static inline bool intel_pmu_has_pebs(void)
return x86_pmu.ds_pebs || x86_pmu.arch_pebs;
}
+static inline bool intel_pmu_has_pebs_lbr(struct pmu *pmu)
+{
+ return x86_pmu.arch_pebs ?
+ !!(hybrid(pmu, arch_pebs_cap).caps & ARCH_PEBS_LBR) :
+ !!x86_pmu.intel_cap.pebs_baseline;
+}
+
#else /* CONFIG_CPU_SUP_INTEL */
static inline void reserve_ds_buffers(void)
--
2.34.1
next prev parent reply other threads:[~2026-10-29 4:47 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-29 4:38 [Patch v5 00/18] perf/x86: Fix multiple LBR sampling issues Dapeng Mi
2026-10-29 4:38 ` [Patch v5 01/18] perf/x86: Disable LBR if x86_pmu.lbr_nr exceeds MAX_LBR_ENTRIES Dapeng Mi
2026-10-29 9:38 ` Peter Zijlstra
2026-10-29 9:56 ` Mi, Dapeng
2026-10-29 10:19 ` Peter Zijlstra
2026-10-29 4:38 ` [Patch v5 02/18] perf/x86/intel: Validate LBR XSAVE state before updating LBR stack Dapeng Mi
2026-10-29 9:40 ` Peter Zijlstra
2026-10-29 10:09 ` Mi, Dapeng
2026-10-29 4:38 ` [Patch v5 03/18] perf/x86/amd/lbr: Limit branch snapshots to valid entries Dapeng Mi
2026-10-29 4:39 ` [Patch v5 04/18] perf/x86/intel/lbr: " Dapeng Mi
2026-10-29 4:39 ` [Patch v5 05/18] perf/x86: Add lbr_enabled to track LBR state Dapeng Mi
2026-10-29 4:39 ` [Patch v5 06/18] perf/x86/amd: Avoid re-enabling PMU and LBR for BPF when disabled Dapeng Mi
2026-10-29 4:39 ` [Patch v5 07/18] perf/x86/intel: Add helper to enable PMU without LBR Dapeng Mi
2026-10-29 4:39 ` [Patch v5 08/18] perf/x86/intel: Avoid re-enabling PMU and LBR for BPF when disabled Dapeng Mi
2026-10-29 4:39 ` [Patch v5 09/18] perf/x86/intel: Keep LBR frozen throughout PMI handling Dapeng Mi
2026-10-29 10:29 ` Peter Zijlstra
2026-10-29 4:39 ` [Patch v5 10/18] perf/x86/intel: Allow LBR read helpers to operate on explicit stacks Dapeng Mi
2026-10-29 10:38 ` Peter Zijlstra
2026-10-29 4:39 ` [Patch v5 11/18] perf/x86/intel: Use a dedicated LBR stack for BPF snapshotting Dapeng Mi
2026-10-29 10:41 ` Peter Zijlstra
2026-10-29 4:39 ` [Patch v5 12/18] perf/x86/intel: Always snapshot live hardware LBR state for BPF Dapeng Mi
2026-10-29 10:56 ` Peter Zijlstra
2026-10-29 4:39 ` [Patch v5 13/18] perf/x86/intel: Refresh LBR stack for non-PEBS LBR events if needed Dapeng Mi
2026-10-29 11:00 ` Peter Zijlstra
2026-10-29 4:39 ` Dapeng Mi [this message]
2026-10-29 4:39 ` [Patch v5 15/18] perf/x86/intel: Clear raw LBR counters in the LBR stack Dapeng Mi
2026-10-29 4:39 ` [Patch v5 16/18] perf/x86/intel: Refill LBR stack for LBR counter events in PMI handler Dapeng Mi
2026-10-29 4:39 ` [Patch v5 17/18] perf/x86/intel: Pass LBR stack size into store_lbr() Dapeng Mi
2026-10-29 4:39 ` [Patch v5 18/18] perf/core: Don't overwrite shared LBR stack depth Dapeng Mi
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