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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BZrJZnf6bhevxS18eMor+qg9FLywdfpAo7FOXdG0F8x7LwHBY0wXYv5buvwBTPpv1xIm0AEGJlU2BmL43aUktHQ5gWLkerkVRa0wS1jOtlOiHfcNHZowr775hNEK5LoT3QiYW3WRv9IBunrHQSc2tp2FijrMf6PBGj6O/o3kDT3SrlvTQ+NuawVZEHf1kQwOqnytQCEuGTTgNj2/J7egEGb9TeYN9XpLDcn5DWaCDxr51OGbLm7Xotah7HtMVg/FukxurlssPwHBFqxLrnJ/97OqB83o4zbwTssTJOqvNc3pbZUwWRAg+W+ddJe4JBYmEmRgra1PK9fOtzJWhPxWB975dnfvGhqZkM70z0Ga+5BzDcBp+thxnJtmcEYHcabgL1ltEVKzOdO0MJY0iPtXdUMHITucHRILPqbH5VNJiSZfdacaAigb2CcQOvxGEU7I X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2026 15:21:15.5650 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c6ca2a1-20de-422a-9065-08df35d04621 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF28EF61683 The soft-recovery, per-ring-reset and IP-block-reset attempts in amdgpu_job_timedout() were only gated on the global amdgpu_gpu_recovery module parameter. Introduce a single can_reset variable that also takes the per-device adev->gpu_recovery_enabled flag into account, and use it for all three attempts instead of reading amdgpu_gpu_recovery directly. Assisted-by: LLM Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 4d363bcfb6a5..0b8d0a79dd45 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -92,6 +92,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) struct drm_wedge_task_info *info = NULL; struct amdgpu_task_info *ti = NULL; struct amdgpu_device *adev = ring->adev; + bool can_reset = amdgpu_gpu_recovery && adev->gpu_recovery_enabled; int idx, r; if (!drm_dev_enter(adev_to_drm(adev), &idx)) { @@ -111,7 +112,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) if (!amdgpu_sriov_vf(adev)) amdgpu_job_core_dump(adev, job); - if (amdgpu_gpu_recovery && + if (can_reset && amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_SOFT_RECOVERY) && amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { dev_err(adev->dev, "ring %s timeout, but soft recovered\n", @@ -130,7 +131,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) } /* attempt a per ring reset */ - if (amdgpu_gpu_recovery && + if (can_reset && amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) && ring->funcs->reset) { dev_err(adev->dev, "Starting %s ring reset\n", @@ -152,7 +153,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) } /* Attempt an IP block soft reset, if supported. */ - if (amdgpu_gpu_recovery && + if (can_reset && amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET)) { r = amdgpu_device_ip_soft_reset(ring, job->hw_fence); if (!r) { -- 2.43.0