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Thu, 29 Oct 2026 08:29:46 -0700 (PDT) Received: from xeon ([188.163.112.62]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c4ca27984f8sm1252166b.80.2026.10.29.08.29.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 08:29:45 -0700 (PDT) From: Svyatoslav Ryhel To: Neil Armstrong , Jessica Zhang , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Svyatoslav Ryhel Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v5 09/11] drm/tegra: rgb: Parameterize configuration based on bus flags Date: Thu, 29 Oct 2026 17:29:07 +0200 Message-ID: <20261029152909.234584-10-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261029152909.234584-1-clamor95@gmail.com> References: <20261029152909.234584-1-clamor95@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Parameterize configuration based on bus flags passed from the bridge or panel. The list of supported flags includes now pixel clock polarity, display enable (DE) polarity, and data alignment. Signed-off-by: Svyatoslav Ryhel --- drivers/gpu/drm/tegra/rgb.c | 39 +++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c index 7dea0cac61233..d8f41d1ca350e 100644 --- a/drivers/gpu/drm/tegra/rgb.c +++ b/drivers/gpu/drm/tegra/rgb.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -106,6 +107,7 @@ static void tegra_rgb_encoder_enable(struct drm_encoder *encoder, struct tegra_output *output = encoder_to_output(encoder); struct tegra_rgb *rgb = to_rgb(output); struct drm_connector_state *conn_state; + struct drm_bridge_state *bridge_state; struct drm_crtc_state *crtc_state; struct drm_connector *connector; struct drm_display_mode *mode; @@ -117,12 +119,21 @@ static void tegra_rgb_encoder_enable(struct drm_encoder *encoder, crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); mode = &crtc_state->adjusted_mode; + /* Get but flags from the bridge state. */ + bridge_state = drm_atomic_get_new_bridge_state(state, output->bridge); + if (bridge_state) + bus_flags = bridge_state->input_bus_cfg.flags; + else + bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | + DRM_BUS_FLAG_DE_HIGH | + DRM_BUS_FLAG_DATA_MSB_TO_LSB; + tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); - /* configure H- and V-sync signal polarities */ + /* configure H- and V-sync and pixel clock signal polarities */ value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); if (mode->flags & DRM_MODE_FLAG_NHSYNC) @@ -135,11 +146,31 @@ static void tegra_rgb_encoder_enable(struct drm_encoder *encoder, else value &= ~BIT(PIN_LVS); + if (bus_flags & DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE) + value &= ~BIT(PIN_LSC0); + else + value |= BIT(PIN_LSC0); + tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); - /* XXX: parameterize? */ - value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB | - DISP_ORDER_RED_BLUE; + /* configure DE signal polarities */ + value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(3)); + + if (bus_flags & DRM_BUS_FLAG_DE_LOW) + value |= BIT(PIN_LSPI); + else + value &= ~BIT(PIN_LSPI); + + tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(3)); + + /* configure DATA order and alignment */ + value = DISP_DATA_FORMAT_DF1P1C | DISP_ORDER_RED_BLUE; + + if (bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB) + value |= DISP_ALIGNMENT_LSB; + else + value &= ~DISP_ALIGNMENT_LSB; + tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); tegra_dc_commit(rgb->dc); -- 2.53.0