From: Sreeraj S Kurup <sreekuttan2156239@gmail.com>
To: sreekuttan2156239@gmail.com
Cc: alim.akhtar@samsung.com, bhelgaas@google.com,
jingoohan1@gmail.com, krzk@kernel.org, kwilczynski@kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-samsung-soc@vger.kernel.org, lpieralisi@kernel.org,
mani@kernel.org, peter.griffin@linaro.org, robh@kernel.org
Subject: [PATCH v2] PCI: exynos: Handle PCIe PHY initialization errors
Date: Thu, 29 Oct 2026 17:54:39 +0000 [thread overview]
Message-ID: <20261029175439.8490-1-sreekuttan2156239@gmail.com> (raw)
In-Reply-To: <20261029131006.2744-1-sreekuttan2156239@gmail.com>
Check the return values of "phy_init()" and "phy_power_on()" to
avoid continuing PCIe host initialization when PHY setup fails.
Track the PHY initialization and power state to ensure cleanup is
performed only when appropriate, avoiding double calls to
"phy_exit()" on probe failure.
Also check the return value of "exynos_pcie_host_init()" during
resume and abort the resume sequence if initialization fails,
disabling the regulators before returning the error.
Signed-off-by: Sreeraj S Kurup <sreekuttan2156239@gmail.com>
---
v2:
- Track PHY initialization and power state to prevent duplicate cleanup.
- Handle host initialization failures during resume.
drivers/pci/controller/dwc/pci-exynos.c | 77 ++++++++++++++++++++++---
1 file changed, 68 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
index e3c05ade381b..f6b87c26ab36 100644
--- a/drivers/pci/controller/dwc/pci-exynos.c
+++ b/drivers/pci/controller/dwc/pci-exynos.c
@@ -55,6 +55,8 @@ struct exynos_pcie {
struct clk_bulk_data *clks;
struct phy *phy;
struct regulator_bulk_data supplies[2];
+ bool phy_initialized;
+ bool phy_powered;
};
static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
@@ -225,13 +227,23 @@ static int exynos_pcie_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct exynos_pcie *ep = to_exynos_pcie(pci);
+ int ret;
pp->bridge->ops = &exynos_pci_ops;
exynos_pcie_assert_core_reset(ep);
- phy_init(ep->phy);
- phy_power_on(ep->phy);
+ ret = phy_init(ep->phy);
+ if (ret)
+ return ret;
+
+ ep->phy_initialized = true;
+
+ ret = phy_power_on(ep->phy);
+ if (ret)
+ return ret;
+
+ ep->phy_powered = true;
exynos_pcie_deassert_core_reset(ep);
exynos_pcie_enable_irq_pulse(ep);
@@ -323,7 +335,16 @@ static int exynos_pcie_probe(struct platform_device *pdev)
return 0;
fail_probe:
- phy_exit(ep->phy);
+ if (ep->phy_powered) {
+ phy_power_off(ep->phy);
+ ep->phy_powered = false;
+ }
+
+ if (ep->phy_initialized) {
+ phy_exit(ep->phy);
+ ep->phy_initialized = false;
+ }
+
regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
return ret;
@@ -335,8 +356,17 @@ static void exynos_pcie_remove(struct platform_device *pdev)
dw_pcie_host_deinit(&ep->pci.pp);
exynos_pcie_assert_core_reset(ep);
- phy_power_off(ep->phy);
- phy_exit(ep->phy);
+
+ if (ep->phy_powered) {
+ phy_power_off(ep->phy);
+ ep->phy_powered = false;
+ }
+
+ if (ep->phy_initialized) {
+ phy_exit(ep->phy);
+ ep->phy_initialized = false;
+ }
+
regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
}
@@ -345,8 +375,17 @@ static int exynos_pcie_suspend_noirq(struct device *dev)
struct exynos_pcie *ep = dev_get_drvdata(dev);
exynos_pcie_assert_core_reset(ep);
- phy_power_off(ep->phy);
- phy_exit(ep->phy);
+
+ if (ep->phy_powered) {
+ phy_power_off(ep->phy);
+ ep->phy_powered = false;
+ }
+
+ if (ep->phy_initialized) {
+ phy_exit(ep->phy);
+ ep->phy_initialized = false;
+ }
+
regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
return 0;
@@ -364,10 +403,30 @@ static int exynos_pcie_resume_noirq(struct device *dev)
return ret;
/* exynos_pcie_host_init controls ep->phy */
- exynos_pcie_host_init(pp);
+ ret = exynos_pcie_host_init(pp);
+ if (ret)
+ goto err_cleanup;
+
dw_pcie_setup_rc(pp);
exynos_pcie_start_link(pci);
- return dw_pcie_wait_for_link(pci);
+ ret = dw_pcie_wait_for_link(pci);
+ if (ret)
+ goto err_cleanup;
+
+ return 0;
+
+err_cleanup:
+ if (ep->phy_powered) {
+ phy_power_off(ep->phy);
+ ep->phy_powered = false;
+ }
+
+ if (ep->phy_initialized) {
+ phy_exit(ep->phy);
+ ep->phy_initialized = false;
+ }
+ regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
+ return ret;
}
static const struct dev_pm_ops exynos_pcie_pm_ops = {
--
2.55.0
next prev parent reply other threads:[~2026-10-29 17:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-29 13:10 [PATCH] PCI: exynos: Handle " Sreeraj S Kurup
2026-10-29 17:54 ` Sreeraj S Kurup [this message]
2026-10-30 15:17 ` [PATCH v3] PCI: exynos: Handle PCIe " Sreeraj S Kurup
2026-10-30 16:36 ` [PATCH v4] " Sreeraj S Kurup
2026-10-30 17:23 ` [PATCH v5] " Sreeraj S Kurup
2026-10-30 18:09 ` [PATCH v6] " Sreeraj S Kurup
2026-10-31 7:01 ` [PATCH v7] " Sreeraj S Kurup
2026-10-31 7:35 ` [PATCH v8] " Sreeraj S Kurup
2026-10-31 9:49 ` [PATCH v9] " Sreeraj S Kurup
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