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Refer to the members of the struct being documented directly instead. Signed-off-by: Beleswar Padhi --- v3: Changelog: 1. None to this patch. Link to v2: https://lore.kernel.org/all/20260930160607.2674980-13-b-padhi@ti.com/ v2: Changelog: 1. None to this patch. Link to v1: https://lore.kernel.org/all/20260929201746.4078803-13-b-padhi@ti.com/ drivers/firmware/ti_sci.h | 126 +++++++++++++++++++------------------- 1 file changed, 63 insertions(+), 63 deletions(-) diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h index 8fccbcd1c9a2c..34f7848073a0e 100644 --- a/drivers/firmware/ti_sci.h +++ b/drivers/firmware/ti_sci.h @@ -813,14 +813,14 @@ struct ti_sci_msg_req_manage_irq { * The ring configuration fields are not valid, and will not be used for * ring configuration, if their corresponding valid bit is zero. * Valid bit usage: - * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo - * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi - * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count - * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode - * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size - * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id - * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid - * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL + * 0 - Valid bit for @addr_lo + * 1 - Valid bit for @addr_hi + * 2 - Valid bit for @count + * 3 - Valid bit for @mode + * 4 - Valid bit for @size + * 5 - Valid bit for @order_id + * 6 - Valid bit for @virtid + * 7 - Valid bit for @asel * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated * @index: ring index to be configured. * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's @@ -1023,23 +1023,23 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { * parameters. The tx channel configuration fields are not valid, and will not * be used for ch configuration, if their corresponding valid bit is zero. * Valid bit usage: - * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err - * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype - * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type - * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size - * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum - * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority - * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos - * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid - * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority - * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo - * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords - * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt - * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count - * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth - * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size - * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype - * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type + * 0 - Valid bit for @tx_pause_on_err + * 1 - Valid bit for @tx_atype + * 2 - Valid bit for @tx_chan_type + * 3 - Valid bit for @tx_fetch_size + * 4 - Valid bit for @txcq_qnum + * 5 - Valid bit for @tx_priority + * 6 - Valid bit for @tx_qos + * 7 - Valid bit for @tx_orderid + * 8 - Valid bit for @tx_sched_priority + * 9 - Valid bit for @tx_filt_einfo + * 10 - Valid bit for @tx_filt_pswords + * 11 - Valid bit for @tx_supr_tdpkt + * 12 - Valid bit for @tx_credit_count + * 13 - Valid bit for @fdepth + * 14 - Valid bit for @tx_burst_size + * 15 - Valid bit for @tx_tdtype + * 16 - Valid bit for @extended_ch_type * * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located * @@ -1153,20 +1153,20 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { * The rx channel configuration fields are not valid, and will not be used for * ch configuration, if their corresponding valid bit is zero. * Valid bit usage: - * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err - * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype - * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type - * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size - * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum - * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority - * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos - * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid - * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority - * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start - * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt - * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short - * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long - * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size + * 0 - Valid bit for @rx_pause_on_err + * 1 - Valid bit for @rx_atype + * 2 - Valid bit for @rx_chan_type + * 3 - Valid bit for @rx_fetch_size + * 4 - Valid bit for @rxcq_qnum + * 5 - Valid bit for @rx_priority + * 6 - Valid bit for @rx_qos + * 7 - Valid bit for @rx_orderid + * 8 - Valid bit for @rx_sched_priority + * 9 - Valid bit for @flowid_start + * 10 - Valid bit for @flowid_cnt + * 11 - Valid bit for @rx_ignore_short + * 12 - Valid bit for @rx_ignore_long + * 14 - Valid bit for @rx_burst_size * * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located * @@ -1197,9 +1197,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { * @flowid_start: UDMAP receive channel additional flows starting index * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG * register. Specifies the starting index for flow IDs the receive channel is to - * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be + * make use of beyond the default flow. flowid_start and @flowid_cnt must be * set as valid and configured together. The starting flow ID set by - * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset + * @flowid_start must be a flow index within the Navigator Subsystem's subset * of flows beyond the default flows statically mapped to receive channels. * The additional flows must be assigned to the host, or a subordinate of the * host, requesting configuration of the receive channel. @@ -1207,10 +1207,10 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { * @flowid_cnt: UDMAP receive channel additional flows count configuration to * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register. * This field specifies how many flow IDs are in the additional contiguous range - * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be + * of legal flow IDs for the channel. @flowid_start and flowid_cnt must be * set as valid and configured together. Disabling the valid_params field bit * for flowid_cnt indicates no flow IDs other than the default are to be - * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt + * allocated and used by the receive channel. @flowid_start plus flowid_cnt * cannot be greater than the number of receive flows in the receive channel's * Navigator Subsystem. The additional flows must be assigned to the host, or a * subordinate of the host, requesting configuration of the receive channel. @@ -1274,25 +1274,25 @@ struct ti_sci_msg_rm_udmap_rx_ch_cfg_req { * Bitfield defining validity of rx flow configuration parameters. The * rx flow configuration fields are not valid, and will not be used for flow * configuration, if their corresponding valid bit is zero. Valid bit usage: - * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present - * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present - * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling - * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type - * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset - * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum - * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi - * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo - * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi - * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo - * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel - * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel - * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel - * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel - * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum - * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum - * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum - * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum - * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location + * 0 - Valid bit for @rx_einfo_present + * 1 - Valid bit for @rx_psinfo_present + * 2 - Valid bit for @rx_error_handling + * 3 - Valid bit for @rx_desc_type + * 4 - Valid bit for @rx_sop_offset + * 5 - Valid bit for @rx_dest_qnum + * 6 - Valid bit for @rx_src_tag_hi + * 7 - Valid bit for @rx_src_tag_lo + * 8 - Valid bit for @rx_dest_tag_hi + * 9 - Valid bit for @rx_dest_tag_lo + * 10 - Valid bit for @rx_src_tag_hi_sel + * 11 - Valid bit for @rx_src_tag_lo_sel + * 12 - Valid bit for @rx_dest_tag_hi_sel + * 13 - Valid bit for @rx_dest_tag_lo_sel + * 14 - Valid bit for @rx_fdq0_sz0_qnum + * 15 - Valid bit for @rx_fdq1_qnum + * 16 - Valid bit for @rx_fdq2_qnum + * 17 - Valid bit for @rx_fdq3_qnum + * 18 - Valid bit for @rx_ps_location * * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is * allocated @@ -1313,7 +1313,7 @@ struct ti_sci_msg_rm_udmap_rx_ch_cfg_req { * * @rx_desc_type: * UDMAP receive flow descriptor type configuration to be programmed into the - * rx_desc_type field field of the flow's RFLOW_RFA register. + * rx_desc_type field of the flow's RFLOW_RFA register. * * @rx_sop_offset: * UDMAP receive flow start of packet offset configuration to be programmed -- 2.34.1