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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2eb3694e20csm567305ad.53.2026.10.29.13.17.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 13:17:55 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Konrad Dybcio , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 06/16] drm/msm/a8xx: Allow nonctx reglist to include GMU regs Date: Thu, 29 Oct 2026 13:16:16 -0700 Message-ID: <20261029201730.151754-7-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261029201730.151754-1-robin.clark@oss.qualcomm.com> References: <20261029201730.151754-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI5MDA3OSBTYWx0ZWRfX7yhEFi6s99HH EUq32Ks0VfZgkltrvRN+66MYdHuPtI1ndSkjSSthbVTyXQXVWBRusBua0XNyX3bZpu6aKxxqXPb iqG8LevQqyN3hRHUA76OOLUYiSJxoRw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI5MDA3OSBTYWx0ZWRfX8FsSIZA4gY5b ELmIqEpprdj7alfdhTkeHQHyVI+YyCA5JaKGCdXcsRvkc0yKsAjTIGpyImAkEoBUdjKPvynJKsu OFOsKPqlgYnLLmHmFlOf58uyibXpikLqfHHeXCBTWWfpE2cf4vCMQNiPYQb2TCSduJ3n/If4YFV PRYsgZ3tXcuyVAHmHll7Nyh3VHY661JAh9/3JjAGP1ire+5KgAQfg3zO+JsBRq176QL81buRvER 73NVxPDU+/4ciXONy6Yz5zx2ZXgMaYYnnWNIi5LJuAJ75PdouOgy17m2fH1FODUibA0GRosl3Db YdVOASLZrmxJ4ujnt9XLj2Rq8tu9Q0DwFMTMH0PVcUgI88dRr1q1REH8M8rdtImmNtvO37XWY5P iy0zqt0Xb+nzx/CSSIuu6Yd266Dt+AaFKQUVmIE5tfL0C/r8MLUREdDG6HA/WERvhrNln7i8S+I UclIOkjvJi/TWvL2Ytw== X-Authority-Analysis: v=2.4 cv=A8T5rKWG c=1 sm=1 tr=0 ts=6ae3a9f5 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=cg0wMmP-TNBUvudz7-YA:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: wmAq5gyNnHXXEw_1sAa4A4Ldl9GivyEp X-Proofpoint-ORIG-GUID: wmAq5gyNnHXXEw_1sAa4A4Ldl9GivyEp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-29_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610290079 >From hw PoV, it's all part of the GPU. But from dt perspective it is it's own device with a separate io space. So we need to detect this and direct writes to the correct place. Signed-off-by: Rob Clark Acked-by: Konrad Dybcio Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 8e91edf16ec2..795c16d88f45 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -370,6 +370,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; const struct a6xx_info *info = adreno_gpu->info->a6xx; const struct adreno_reglist_pipe *regs = info->nonctxt_reglist; unsigned int pipe_id, i; @@ -389,7 +390,11 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) *gmem_protect = regs[i].value; - gpu_write(gpu, regs[i].offset, regs[i].value); + if ((regs[i].offset << 2) >= gmu->mmio_offset) { + gmu_write(gmu, regs[i].offset, regs[i].value); + } else { + gpu_write(gpu, regs[i].offset, regs[i].value); + } } a8xx_aperture_release(gpu, flags); -- 2.56.0