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The driver advances the command queue's write pointer, which publishes the command, and then writes NV_PGSP_QUEUE_HEAD, which interrupts the GSP so that it reads the queue. In msgq v0, the write pointer is in the queue's shared-memory header, so the two steps are two writes. In msgq v2, the write pointer is NV_PGSP_QUEUE_HEAD itself, so one register write does both. Nova-core split the two steps across two types. The queue memory type advanced the write pointer in shared memory, and the command queue type then rang the doorbell through a BAR0 mapping that it held for that one purpose. Move the BAR0 mapping into the queue memory type, and ring the doorbell at the end of the operation that advances the write pointer in order to prepare for the switch to msgq v2. No functional change intended. [ acourbot: slightly reword and trim commit message. ] Assisted-by: LLM Signed-off-by: John Hubbard Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gsp/cmdq.rs | 52 +++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs index d51797a0a782..a271114fb54c 100644 --- a/drivers/gpu/nova-core/gsp/cmdq.rs +++ b/drivers/gpu/nova-core/gsp/cmdq.rs @@ -157,11 +157,16 @@ unsafe impl FromBytes for GspMem {} /// pointer and the GSP read pointer. This region is returned by [`Self::driver_write_area`]. /// * The driver owns (i.e. can read from) the part of the GSP message queue between the CPU read /// pointer and the GSP write pointer. This region is returned by [`Self::driver_read_area`]. -struct DmaGspMem<'a>(Coherent<'a, GspMem>); +struct DmaGspMem<'a> { + /// The queues, mapped for the GSP. + mem: Coherent<'a, GspMem>, + /// MMIO mapping of PCI BAR0, for the doorbell register. + bar: Bar0<'a>, +} impl<'a> DmaGspMem<'a> { /// Allocate a new instance and map it for `dev`. - fn new(dev: &'a device::Device) -> Result { + fn new(dev: &'a device::Device, bar: Bar0<'a>) -> Result { const MSGQ_SIZE: u32 = num::usize_into_u32::<{ size_of::() }>(); const RX_HDR_OFF: u32 = num::usize_into_u32::<{ mem::offset_of!(Msgq, rx) }>(); @@ -172,7 +177,7 @@ fn new(dev: &'a device::Device) -> Result { let gsp_mem: Coherent<'_, _> = gsp_mem.into(); PteArray::init(io_project!(gsp_mem, .ptes), gsp_mem.dma_address())?; - Ok(Self(gsp_mem)) + Ok(Self { mem: gsp_mem, bar }) } /// Returns the region of the CPU message queue that the driver is currently allowed to write @@ -185,7 +190,7 @@ fn new(dev: &'a device::Device) -> Result { let rx = self.gsp_read_ptr(); // Pointer to the first entry of the CPU message queue. - let data = ptr::project!(mut self.0.as_mut_ptr(), .cpuq.msgq.data[build: 0]); + let data = ptr::project!(mut self.mem.as_mut_ptr(), .cpuq.msgq.data[build: 0]); let (tail_end, wrap_end) = if rx == 0 { // The write area is non-wrapping, and stops at the second-to-last entry of the command @@ -247,7 +252,7 @@ fn driver_write_area_size(&self) -> usize { let rx = self.cpu_read_ptr(); // Pointer to the first entry of the GSP message queue. - let data = ptr::project!(self.0.as_ptr(), .gspq.msgq.data[build: 0]); + let data = ptr::project!(self.mem.as_ptr(), .gspq.msgq.data[build: 0]); let (tail_end, wrap_end) = if rx <= tx { // Read area is non-wrapping and stops right before `tx`. @@ -331,7 +336,7 @@ fn allocate_command(&mut self, size: usize, timeout: Delta) -> Result u32 { - let ptr = MsgqTxHeader::write_ptr(io_project!(self.0, .gspq.tx)) % MSGQ_NUM_PAGES; + let ptr = MsgqTxHeader::write_ptr(io_project!(self.mem, .gspq.tx)) % MSGQ_NUM_PAGES; // ORDERING: LOAD->LOAD ordering needed to order `gsp_write_ptr` read before data read. dma_mb(Read); @@ -345,7 +350,7 @@ fn gsp_write_ptr(&self) -> u32 { // // - The returned value is within `0..MSGQ_NUM_PAGES`. fn gsp_read_ptr(&self) -> u32 { - let ptr = MsgqRxHeader::read_ptr(io_project!(self.0, .gspq.rx)) % MSGQ_NUM_PAGES; + let ptr = MsgqRxHeader::read_ptr(io_project!(self.mem, .gspq.rx)) % MSGQ_NUM_PAGES; // ORDERING: LOAD->STORE ordering needed to order `gsp_read_ptr` read before data write. dma_mb(Full); @@ -359,7 +364,7 @@ fn gsp_read_ptr(&self) -> u32 { // // - The returned value is within `0..MSGQ_NUM_PAGES`. fn cpu_read_ptr(&self) -> u32 { - MsgqRxHeader::read_ptr(io_project!(self.0, .cpuq.rx)) % MSGQ_NUM_PAGES + MsgqRxHeader::read_ptr(io_project!(self.mem, .cpuq.rx)) % MSGQ_NUM_PAGES } // Informs the GSP that it can send `elem_count` new pages into the message queue. @@ -367,7 +372,7 @@ fn advance_cpu_read_ptr(&mut self, elem_count: u32) { // ORDERING: LOAD->STORE ordering needed to order `cpu_read_ptr` write after data read. dma_mb(Full); - let rx = io_project!(self.0, .cpuq.rx); + let rx = io_project!(self.mem, .cpuq.rx); let rptr = MsgqRxHeader::read_ptr(rx).wrapping_add(elem_count) % MSGQ_NUM_PAGES; MsgqRxHeader::set_read_ptr(rx, rptr) } @@ -378,17 +383,24 @@ fn advance_cpu_read_ptr(&mut self, elem_count: u32) { // // - The returned value is within `0..MSGQ_NUM_PAGES`. fn cpu_write_ptr(&self) -> u32 { - MsgqTxHeader::write_ptr(io_project!(self.0, .cpuq.tx)) % MSGQ_NUM_PAGES + MsgqTxHeader::write_ptr(io_project!(self.mem, .cpuq.tx)) % MSGQ_NUM_PAGES } - // Informs the GSP that it can process `elem_count` new pages from the command queue. + // Publishes `elem_count` more pages of the command queue to the GSP and rings the doorbell. fn advance_cpu_write_ptr(&mut self, elem_count: u32) { // ORDERING: STORE->STORE ordering needed to order `cpu_write_ptr` write after data write. dma_mb(Write); - let tx = io_project!(self.0, .cpuq.tx); + let tx = io_project!(self.mem, .cpuq.tx); let wptr = MsgqTxHeader::write_ptr(tx).wrapping_add(elem_count) % MSGQ_NUM_PAGES; MsgqTxHeader::set_write_ptr(tx, wptr); + + // A write to the head register interrupts the GSP. The pointer itself is in the + // shared-memory header, so the value written does not matter. + self.bar.write( + Array::at(0), + regs::NV_PGSP_QUEUE_HEAD::zeroed().with_address(0u32), + ); } } @@ -468,13 +480,12 @@ pub(crate) fn new( bar: Bar0<'cmdq>, ) -> impl PinInit + 'cmdq { pin_init_scope(move || { - let gsp_mem = DmaGspMem::new(dev)?; + let gsp_mem = DmaGspMem::new(dev, bar)?; Ok(try_pin_init!(Self { - dma_addr: gsp_mem.0.dma_address(), + dma_addr: gsp_mem.mem.dma_address(), inner <- new_mutex!(CmdqInner { dev, - bar, gsp_mem, seq: 0, }), @@ -495,14 +506,6 @@ fn calculate_checksum>(it: T) -> u32 { ((sum64 >> 32) as u32) ^ (sum64 as u32) } - /// Notifies the GSP that we have updated the command queue pointers. - fn notify_gsp(bar: Bar0<'_>) { - bar.write( - Array::at(0), - regs::NV_PGSP_QUEUE_HEAD::zeroed().with_address(0u32), - ); - } - /// Logs and consumes every message the GSP has already posted, and returns without waiting for /// more. /// @@ -522,8 +525,6 @@ pub(crate) fn drain(&self) -> Result { struct CmdqInner<'a> { /// Device this command queue belongs to. dev: &'a device::Device, - /// MMIO mapping of PCI BAR0, for writing the GSP doorbell. - bar: Bar0<'a>, /// Current command sequence number. seq: u32, /// Memory area shared with the GSP for communicating commands and messages. @@ -571,7 +572,6 @@ fn send_command_element(&mut self, command: E) -> Result { let elem_count = dst.header.element_count(); self.seq += 1; self.gsp_mem.advance_cpu_write_ptr(elem_count); - Cmdq::notify_gsp(self.bar); Ok(()) } -- 2.56.0