From: Krzysztof Kozlowski <krzk@kernel.org>
To: Douglas Anderson <dianders@chromium.org>
Cc: "Jassi Brar" <jassisinghbrar@gmail.com>,
"Joonwon Kang" <joonwonkang@google.com>,
"Subhash Jadavani" <sjadavani@google.com>,
"Peter Griffin" <peter.griffin@linaro.org>,
"Lucas Wei" <lucaswei@google.com>,
"André Draszik" <andre.draszik@linaro.org>,
"Tudor Ambarus" <tudor.ambarus@linaro.org>,
"Brian Norris" <briannorris@chromium.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Rob Herring" <robh@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v2 3/4] dt-bindings: mailbox: goog-mba: Add goog-mba mailbox bindings
Date: Fri, 30 Oct 2026 11:48:42 +0100 [thread overview]
Message-ID: <20261030-terrific-quartz-bumblebee-e36da1@quoll> (raw)
In-Reply-To: <20261023165211.v2.3.Ia186a29119b4b5c409815b755e0c2c3965b0495f@changeid>
On Fri, Oct 23, 2026 at 04:52:20PM -0700, Douglas Anderson wrote:
> +properties:
> + compatible:
> + const: google,lga-mailbox-array
> +
> + reg:
> + minItems: 1
> + items:
> + - description: Host registers (not accessible to client)
> + - description: Global registers (not present on newer IP blocks)
That's still confusing. Last time you said:
1. You identified 4x instances of MBA
2. Each of the instance has global registers (quotting: "Each of these 4
MBA instances has its own "global" registers."), then why does the
binding say otherwise?
You repeat here again "newer IP blocks" so how many versions does your SoC have?
> +
> + ranges: true
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> +patternProperties:
> + "^mailbox@[0-9a-f]+$":
> + type: object
> + description:
> + Each sub-node is a single-channel mailbox.
> +
> + properties:
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + "#mbox-cells":
> + const: 0
> +
> + google,rx-payload-words:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maximum: 256
> + default: 0
> + description:
> + The number of 32-bit words in each mailbox message from the remote
> + processor. May be 0 for doorbell-only. If not specified this is
> + assumed to be 0.
> +
> + google,tx-payload-words:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maximum: 256
> + default: 0
> + description:
> + For queue-mode only, the number of 32-bit words in each message we
> + send to the remote processor. If not specified, this is assumed to
> + be 0. This is only for queue mode where we need to divide up the
> + message buffer into chunks.
> +
> + google,mba-queue-mode:
> + type: boolean
> + description:
> + The remote processor is expecting the shared memory to be treated
> + as a circular queue and that there may be several outstanding
> + messages at once. Only usable on instances with counted doorbell
> + interrupts.
> +
> + dependencies:
> + google,tx-payload-words: ['google,mba-queue-mode']
> +
> + required:
> + - reg
> + - interrupts
> + - "#mbox-cells"
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - ranges
> + - reg
> + - "#address-cells"
> + - "#size-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mailbox-array@5240000 {
> + compatible = "google,lga-mailbox-array";
> + reg = <0x0 0x05240000 0x0 0x00010000>,
> + <0x0 0x05250000 0x0 0x00010000>;
> + ranges = <0x0 0x0 0x05260000 0x00020000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + mailbox@0 {
> + reg = <0x0000 0x1000>;
> + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>;
> +
> + #mbox-cells = <0>;
> +
> + google,tx-payload-words = <4>;
> + google,mba-queue-mode;
> + };
> +
> + mailbox@1000 {
> + reg = <0x1000 0x1000>;
> + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> +
Please make the example complete. Last time you wrote:
"If we tried to represent the mailbox array as a single mailbox with a
bunch of channels, each instance would have a different number of
"reg" entries and a different number of interrupts."
and I do not see that. I see each instance having exactly one reg entry,
exactly one interrupt with difference in RX and TX.
The DTS here:
https://lore.kernel.org/all/20261026144346.1.Iaf8214205f496225013f482f6e0035e89ac624f2@changeid/
has the same.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-10-30 10:48 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-23 23:52 [PATCH v2 0/4] mailbox: Improve the mbox core then introduce the goog-mba driver Douglas Anderson
2026-10-23 23:52 ` [PATCH v2 1/4] mailbox: Allow #mbox-cells = <0> without specifying a custom xlate Douglas Anderson
2026-10-23 23:52 ` [PATCH v2 2/4] mailbox: Find a matching mailbox by fwnode rather than device Douglas Anderson
2026-10-23 23:52 ` [PATCH v2 3/4] dt-bindings: mailbox: goog-mba: Add goog-mba mailbox bindings Douglas Anderson
2026-10-30 10:48 ` Krzysztof Kozlowski [this message]
2026-10-30 23:33 ` Doug Anderson
2026-10-23 23:52 ` [PATCH v2 4/4] mailbox: goog-mba: Introduce the goog-mba mailbox driver Douglas Anderson
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