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[24.85.96.29]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cdb0981c5desm111713a12.27.2026.10.29.20.29.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 20:29:52 -0700 (PDT) From: Mahmoud Abumandour To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mahmoud Abumandour Subject: [PATCH v2 1/2] KVM: nVMX: Don't let L2's LMSW modify CR0 bits owned by L1 Date: Thu, 29 Oct 2026 20:29:36 -0700 Message-Id: <20261030032937.2813-2-ma.mandourr@gmail.com> X-Mailer: git-send-email 2.40.1.windows.1 In-Reply-To: <20261030032937.2813-1-ma.mandourr@gmail.com> References: <20261030032937.2813-1-ma.mandourr@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable When L2's LMSW exits to L0 but not to L1, emulate it through=0D handle_set_cr0(), as is done for MOV to CR0. kvm_lmsw() ignores=0D vmcs12's CR0 guest/host mask, so L2 could change CR0 bits that L1 owns,=0D e.g. clear TS, and read their effective values instead of the read shadow.= =0D =0D Fixes: eeadf9e7558c ("KVM: nVMX: Handling of CR0 and CR4 modifying instruct= ions")=0D Signed-off-by: Mahmoud Abumandour =0D ---=0D arch/x86/kvm/vmx/vmx.c | 15 +++++++++++++++=0D 1 file changed, 15 insertions(+)=0D =0D diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c=0D index b341af4c60..3633496299 100644=0D --- a/arch/x86/kvm/vmx/vmx.c=0D +++ b/arch/x86/kvm/vmx/vmx.c=0D @@ -5748,6 +5748,21 @@ static int handle_cr(struct kvm_vcpu *vcpu)=0D case 3: /* lmsw */=0D val =3D (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;=0D trace_kvm_cr_write(0, (kvm_read_cr0_bits(vcpu, ~0xful) | val));=0D + if (is_guest_mode(vcpu)) {=0D + struct vmcs12 *vmcs12 =3D get_vmcs12(vcpu);=0D + unsigned long mask =3D vmcs12->cr0_guest_host_mask;=0D + unsigned long cr0;=0D +=0D + /*=0D + * LMSW leaves the bits L1 owns unmodified, as does a MOV=0D + * to CR0 that writes their read shadow values. Emulate=0D + * it as that MOV: L2's view of CR0 with LMSW's bits.=0D + */=0D + cr0 =3D (kvm_read_cr0(vcpu) & ~mask) |=0D + (vmcs12->cr0_read_shadow & mask);=0D + err =3D handle_set_cr0(vcpu, (cr0 & ~0x0eul) | val);=0D + return kvm_complete_insn_gp(vcpu, err);=0D + }=0D kvm_lmsw(vcpu, val);=0D =0D return kvm_skip_emulated_instruction(vcpu);=0D -- =0D 2.25.1=0D =0D