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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 52e796924; Fri, 30 Oct 2026 14:49:29 +0800 (GMT+08:00) From: Damon Ding To: Sandy Huang , Heiko Stuebner , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Andrzej Hajda , Robert Foss Cc: Neil Armstrong , Manivannan Sadhasivam , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Dave Jones , Dmitry Baryshkov , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Damon Ding Subject: [PATCH v4 2/6] dt-bindings: phy: Add rockchip,rk3568-edp-phy Date: Fri, 30 Oct 2026 14:49:01 +0800 Message-Id: <20261030064905.2248999-3-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261030064905.2248999-1-damon.ding@rock-chips.com> References: <20261030064905.2248999-1-damon.ding@rock-chips.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-HM-Tid: 0aa18b9216be03a8kunme14bef99793f3 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1kYFggdWUFKV1ktWUFJV1kPCRoVCBIfWUFZGkJMGFZLGE8fSB1MHh gaHR5WFRQJFhoXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0 tIVUpLSEpKQk1VSktLVUpCWQY+ DKIM-Signature: a=rsa-sha256; b=QfaKInEi50Xe9+Q4iIYs66NJ6q33E2lYOa3LkMcB++LjekVsRHq9abqZvSU9HOd9j1NVhuV1zhKbxRKvkgTdmOj0rKxqu0ZmyFVjLTd/TR/3uMmyZA0Ox6sscPaYqd9X/4frrAtXJCN83m6gvfPet6svNqCJXWeTUtL3ORPiXQE=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=AgPYeLEugJgoEq+vG9KeV8ZAJVbryREVsFUQ1Fma0vY=; h=date:mime-version:subject:message-id:from; Document the eDP transmitter PHY with NaNeng IP block found on the RK3568 SoC. The PHY has its own register window inside the eDP PHY GRF, so its node is modeled as a child of the eDP PHY GRF syscon with a reg property describing that window. Also add the "rockchip,rk3568-edp-phy-grf" compatible and the phy node reference to the Rockchip GRF schema. Signed-off-by: Damon Ding --- Changes in v4: - Add the reg entry for the PHY node and the ranges/#address-cells/ #size-cells for the parent syscon node. --- .../bindings/phy/rockchip,rk3568-edp-phy.yaml | 68 +++++++++++++++++++ .../devicetree/bindings/soc/rockchip/grf.yaml | 20 ++++++ 2 files changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml new file mode 100644 index 000000000000..b78da00ffefd --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3568-edp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip eDP Transmitter PHY with NaNeng IP block + +maintainers: + - Damon Ding + - Heiko Stuebner + +description: + On the RK3568 SoC the eDP PHY is controlled through the eDP PHY GRF + registers, therefore the PHY node is expected to be a child of the + eDP PHY GRF syscon node. + +properties: + compatible: + const: rockchip,rk3568-edp-phy + + reg: + maxItems: 1 + description: PHY registers within the eDP PHY GRF. + + clocks: + maxItems: 1 + + clock-names: + const: refclk + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + edp_phy_grf: syscon@fdcb0000 { + compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdcb0000 0x0 0x8000>; + clocks = <&cru PCLK_EDPPHY_GRF>; + ranges = <0x0 0x0 0xfdcb0000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + edp_phy: phy@0 { + compatible = "rockchip,rk3568-edp-phy"; + reg = <0x0 0x100>; + clocks = <&pmucru XIN_OSC0_EDPPHY_G>; + clock-names = "refclk"; + #phy-cells = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 7bcb4e2f47ec..c089bd014003 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -93,6 +93,7 @@ properties: - rockchip,rk3399-grf - rockchip,rk3399-pmugrf - rockchip,rk3562-pmu-grf + - rockchip,rk3568-edp-phy-grf - rockchip,rk3568-grf - rockchip,rk3568-pmugrf - rockchip,rk3576-ioc-grf @@ -119,6 +120,8 @@ properties: "#size-cells": const: 1 + ranges: true + required: - compatible - reg @@ -156,6 +159,22 @@ allOf: $ref: /schemas/phy/rockchip,rk3288-dp-phy.yaml# unevaluatedProperties: false + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-edp-phy-grf + + then: + required: + - "#address-cells" + - "#size-cells" + patternProperties: + "^phy@[0-9a-f]+$": + type: object + $ref: /schemas/phy/rockchip,rk3568-edp-phy.yaml# + unevaluatedProperties: false + - if: properties: compatible: @@ -309,6 +328,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3568-edp-phy-grf - rockchip,rk3576-dcphy-grf - rockchip,rk3576-vo1-grf - rockchip,rk3588-vo-grf -- 2.34.1