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Fri, 30 Oct 2026 00:36:47 -0700 (PDT) Received: from thinkpad.hgw.local ([159.146.110.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e71b728f9sm1721764f8f.10.2026.10.30.00.36.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 00:36:46 -0700 (PDT) From: =?UTF-8?q?Yal=C3=A7=C4=B1n=20Can?= To: Michael Turquette , Stephen Boyd , Heiko Stuebner Cc: Brian Masney , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: rockchip: rk3066: uart0/1 pclk comes from hclk_ahb2apb Date: Fri, 30 Oct 2026 10:36:38 +0300 Message-ID: <20261030073638.164388-1-ylcncn@gmail.com> X-Mailer: git-send-email 2.47.3 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On rk3066a, uart0 (0x10124000) and uart1 (0x10126000) sit behind the AHB-to-APB bridge of the cpu bus, as on rk3188, but their pclk gates name pclk_cpu as parent. Nothing then holds hclk_ahb2apb (CLKGATE_CON4 bit 9), so it is switched off as unused at late init and both UARTs read back as all zeros: 8250 autoconfig reports PORT_UNKNOWN for uart0 and a serdev Bluetooth controller on it (brcm,bcm4330-bt) times out on every command. The vendor 3.0 kernel uses the same parent, but models ahb2apb as a divider without a gate, so it is never turned off there. Make hclk_ahb2apb the parent of pclk_uart0/1, as the rk3188 table already does. Tested on an RK3066a board (MK808B, BCM4330 Bluetooth on uart0): before, CLKGATE_CON4 reads 0x6200, uart0 registers read 0 and ttyS0 is PORT_UNKNOWN; clearing bit 9 by hand makes it probe as a 16550A. With this patch uart0 probes as a 16550A at boot, hci_bcm loads its firmware patch, and LE and BR/EDR scans find other devices. uart1 is not wired on this board and was not tested. Fixes: 2c14736c75db ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks") Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Yalçın Can --- drivers/clk/rockchip/clk-rk3188.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 318c8ddc8..680c33a62 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -649,8 +649,9 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS), GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS), - GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), - GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), + /* uart0/1 sit behind the AHB-to-APB bridge, as on rk3188 */ + GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS), -- 2.47.3