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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF0000231F.mail.protection.outlook.com (10.167.242.235) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.569.4 via Frontend Transport; Fri, 30 Oct 2026 08:24:22 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Fri, 30 Oct 2026 03:24:21 -0500 Received: from xhdipdslab46.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.53 via Frontend Transport; Fri, 30 Oct 2026 03:24:19 -0500 From: Abhijit Gangurde To: , CC: , , , , "Abhijit Gangurde" , Keith Lucas , Subject: [for-next 1/1] RDMA/ionic: Use a linear QID space when udma_shift is zero Date: Fri, 30 Oct 2026 13:54:02 +0530 Message-ID: <20261030082402.841751-1-abhijit.gangurde@amd.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231F:EE_|IA0PR12MB8228:EE_ X-MS-Office365-Filtering-Correlation-Id: b72b9629-c5f0-49e0-4c1b-08df365f3389 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|376014|1800799024|18002099003|13003099007|56012099006|11063799006|261021135927099003|10067099003|261021123027099003|261021121427099003|261009223027099003; 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A value of zero means the queues are not striped across two UDMAs, so the QID space is linear and the device has one UDMA. The interleaved bitid/qid transform treats bit 0 as the UDMA selector when the group shift is zero. QID 1 then becomes bitid 1 << half_qid_shift, and freeing that QID releases the wrong allocator index. Skip the transform and select one UDMA so QP and CQ allocation uses the QID directly. Fixes: e8521822c733 ("RDMA/ionic: Register device ops for control path") Reported-by: Keith Lucas Link: https://lore.kernel.org/r/20261021161651.4020222-1-haakon.bugge@oracle.com Cc: stable@vger.kernel.org # 6.18 Signed-off-by: Abhijit Gangurde --- drivers/infiniband/hw/ionic/ionic_lif_cfg.c | 2 +- drivers/infiniband/hw/ionic/ionic_res.h | 23 ++++++++++++++------- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/infiniband/hw/ionic/ionic_lif_cfg.c b/drivers/infiniband/hw/ionic/ionic_lif_cfg.c index 66cee57442e7..a3ee86b56037 100644 --- a/drivers/infiniband/hw/ionic/ionic_lif_cfg.c +++ b/drivers/infiniband/hw/ionic/ionic_lif_cfg.c @@ -84,7 +84,7 @@ void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg) cfg->cq_qtype = ident->rdma.cq_qtype.qtype; cfg->eq_qtype = ident->rdma.eq_qtype.qtype; cfg->udma_qgrp_shift = ident->rdma.udma_shift; - cfg->udma_count = 2; + cfg->udma_count = cfg->udma_qgrp_shift ? 2 : 1; cfg->max_stride = ident->rdma.max_stride; cfg->rcq_sign_bit = ident->rdma.rcq_sign_bit; diff --git a/drivers/infiniband/hw/ionic/ionic_res.h b/drivers/infiniband/hw/ionic/ionic_res.h index 46c8c584bd9a..c480865dced5 100644 --- a/drivers/infiniband/hw/ionic/ionic_res.h +++ b/drivers/infiniband/hw/ionic/ionic_res.h @@ -125,10 +125,14 @@ static inline void ionic_resid_put(struct ionic_resid_bits *resid, int id) static inline u32 ionic_bitid_to_qid(u32 bitid, u8 qgrp_shift, u8 half_qid_shift) { - u32 udma_bit = - (bitid & BIT(half_qid_shift)) >> (half_qid_shift - qgrp_shift); - u32 grp_bits = (bitid & GENMASK(half_qid_shift - 1, qgrp_shift)) << 1; - u32 idx_bits = bitid & (BIT(qgrp_shift) - 1); + u32 udma_bit, grp_bits, idx_bits; + + if (!qgrp_shift) + return bitid; + + udma_bit = (bitid & BIT(half_qid_shift)) >> (half_qid_shift - qgrp_shift); + grp_bits = (bitid & GENMASK(half_qid_shift - 1, qgrp_shift)) << 1; + idx_bits = bitid & (BIT(qgrp_shift) - 1); return grp_bits | udma_bit | idx_bits; } @@ -145,9 +149,14 @@ static inline u32 ionic_bitid_to_qid(u32 bitid, u8 qgrp_shift, */ static inline u32 ionic_qid_to_bitid(u32 qid, u8 qgrp_shift, u8 half_qid_shift) { - u32 udma_bit = (qid & BIT(qgrp_shift)) << (half_qid_shift - qgrp_shift); - u32 grp_bits = (qid & GENMASK(half_qid_shift, qgrp_shift + 1)) >> 1; - u32 idx_bits = qid & (BIT(qgrp_shift) - 1); + u32 udma_bit, grp_bits, idx_bits; + + if (!qgrp_shift) + return qid; + + udma_bit = (qid & BIT(qgrp_shift)) << (half_qid_shift - qgrp_shift); + grp_bits = (qid & GENMASK(half_qid_shift, qgrp_shift + 1)) >> 1; + idx_bits = qid & (BIT(qgrp_shift) - 1); return udma_bit | grp_bits | idx_bits; } -- 2.43.0