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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from BL0PR12MB2370.namprd12.prod.outlook.com (2603:10b6:207:47::27) by CH3PR12MB8457.namprd12.prod.outlook.com (2603:10b6:610:154::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.569.9; Fri, 30 Oct 2026 09:59:36 +0000 Received: from BL0PR12MB2370.namprd12.prod.outlook.com ([fe80::86cf:c3ec:2cf5:74c8]) by BL0PR12MB2370.namprd12.prod.outlook.com ([fe80::86cf:c3ec:2cf5:74c8%5]) with mapi id 15.21.0569.008; Fri, 30 Oct 2026 09:59:36 +0000 From: Richard Cheng To: dave@stgolabs.net, jic23@kernel.org, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com Cc: iweiny@kernel.org, ming.li@zohomail.com, icheng@nvidia.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, kaihengf@nvidia.com, kobak@nvidia.com, newtonl@nvidia.com, kristinc@nvidia.com Subject: [PATCH] cxl/port: Fix endpoint RAS error unmasking Date: Fri, 30 Oct 2026 17:59:23 +0800 Message-ID: <20261030095923.46051-1-icheng@nvidia.com> X-Mailer: git-send-email 2.50.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SI2PR06CA0005.apcprd06.prod.outlook.com (2603:1096:4:186::12) To BL0PR12MB2370.namprd12.prod.outlook.com (2603:10b6:207:47::27) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL0PR12MB2370:EE_|CH3PR12MB8457:EE_ X-MS-Office365-Filtering-Correlation-Id: 7117f87c-708c-48d8-091b-08df366c80d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|366016|18002099003|261009223027099003|261028144727099003|261022075727099003|261021121427099003|10067099003|261021123027099003|261022105027099003|261026140227099003|11063799006|56012099006; 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If the topology use cxl_memdev as uport_dev, the PCI check will fail and CXL RAS masks remain set. Resolve memdev uports to their parent dev and verify the device is PCI. Fixes: dab7162d0ae7 ("cxl/port: Move endpoint component register management to cxl_port") Signed-off-by: Richard Cheng --- Reproducer is a QEMU Type-3 guest 1. Ensure no CXL region is active and PCIe AER is enabled. 2. Restore the emulated RAS registers to their reset masks. 3. Reprobe cxl_pci and read the masks again. ``` BDF=$(basename "$(dirname "$(readlink -f /sys/bus/cxl/devices/mem0)")") BAR0=$(awk 'NR == 1 { print $1 }' /sys/bus/pci/devices/$BDF/resource) UNC_MASK=$(printf '0x%x' $((BAR0 + 0x1084))) COR_MASK=$(printf '0x%x' $((BAR0 + 0x1090))) busybox devmem "$UNC_MASK" 32 0x1cfff busybox devmem "$COR_MASK" 32 0x7f echo "$BDF" > /sys/bus/pci/drivers/cxl_pci/unbind echo "$BDF" > /sys/bus/pci/drivers/cxl_pci/bind udevadm settle busybox devmem "$UNC_MASK" 32 busybox devmem "$COR_MASK" 32 ``` Before the fix, the masks remain 0x1cfff and 0x7f. After the fix, both masks read as zero. Best regards, Richard Cheng. --- drivers/cxl/port.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index c12fd0b89883..c48216e5078f 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -74,15 +74,18 @@ static int cxl_switch_port_probe(struct cxl_port *port) static int cxl_ras_unmask(struct cxl_port *port) { + struct device *host = port->uport_dev; struct pci_dev *pdev; void __iomem *addr; u32 orig_val, val, mask; u16 cap; int rc; - if (!dev_is_pci(port->uport_dev)) + if (is_cxl_memdev(host)) + host = host->parent; + if (!host || !dev_is_pci(host)) return 0; - pdev = to_pci_dev(port->uport_dev); + pdev = to_pci_dev(host); if (!port->regs.ras) { pci_dbg(pdev, "No RAS registers.\n"); base-commit: d135ab453a7400a34930bdda1ef4bdc8acfac80e -- 2.43.0