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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from BL0PR12MB2370.namprd12.prod.outlook.com (2603:10b6:207:47::27) by CH3PR12MB8457.namprd12.prod.outlook.com (2603:10b6:610:154::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.569.9; Fri, 30 Oct 2026 10:00:00 +0000 Received: from BL0PR12MB2370.namprd12.prod.outlook.com ([fe80::86cf:c3ec:2cf5:74c8]) by BL0PR12MB2370.namprd12.prod.outlook.com ([fe80::86cf:c3ec:2cf5:74c8%5]) with mapi id 15.21.0569.008; Fri, 30 Oct 2026 10:00:00 +0000 From: Richard Cheng To: dave@stgolabs.net, jic23@kernel.org, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com Cc: iweiny@kernel.org, ming.li@zohomail.com, icheng@nvidia.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, kaihengf@nvidia.com, kobak@nvidia.com, newtonl@nvidia.com, kristinc@nvidia.com Subject: [PATCH] cxl/port: Unmask AER internal errors for VH endpoints Date: Fri, 30 Oct 2026 17:59:51 +0800 Message-ID: <20261030095951.46080-1-icheng@nvidia.com> X-Mailer: git-send-email 2.50.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SI2PR02CA0035.apcprd02.prod.outlook.com (2603:1096:4:195::22) To BL0PR12MB2370.namprd12.prod.outlook.com (2603:10b6:207:47::27) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL0PR12MB2370:EE_|CH3PR12MB8457:EE_ X-MS-Office365-Filtering-Correlation-Id: 92442fa0-f9e6-41c4-0378-08df366c8dd9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|366016|6133799003|18002099003|3023799007|261009223027099003|261022075727099003|261021121427099003|10067099003|261021123027099003|261026121527099003|11063799006|56012099006|260925022911599003|260925021911599003|260925021311599003; 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Unmasking the endpoint's CXL RAS register alone leaves the AER internal errors masked, thus the notification can't reach the Root Port. Unmask AER internal errors during native endpoint RAS setup for VH devices. Allow cxl_port to use pci_aer_unmask_internal_errors() through its module-restricted export. Verified with QEMU mem-data-ecc injection: the Root Port AER interrupt fires, the CXL correctable-error trace is emitted, and the endpoint's CorrIntErr counter increments. Signed-off-by: Richard Cheng --- drivers/cxl/port.c | 7 +++++++ drivers/pci/pcie/aer.c | 3 ++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index c48216e5078f..c94a310061b0 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -121,6 +121,13 @@ static int cxl_ras_unmask(struct cxl_port *port) orig_val, val); } + /* + * RCH errors are reported by the RCEC. VH endpoints report CXL + * protocol errors as PCIe AER internal errors. + */ + if (!is_cxl_restricted(pdev)) + pci_aer_unmask_internal_errors(pdev); + return 0; } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index db4f607f889c..94eca22422b7 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1287,7 +1287,8 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev) * Internal errors are too device-specific to enable generally, however for CXL * their behavior is standardized for conveying CXL protocol errors. */ -EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core"); +EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, + "cxl_core,cxl_port"); #ifdef CONFIG_CXL_RAS bool is_aer_internal_error(struct aer_err_info *info) base-commit: f0c48323b0402349530abc60ea908b5f5f40c395 -- 2.43.0