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Fri, 30 Oct 2026 07:10:21 -0700 (PDT) Received: from localhost.localdomain ([2001:861:39c2:e340:24ce:a263:4d8:38f1]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e71ba53d7sm5181973f8f.53.2026.10.30.07.10.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 07:10:19 -0700 (PDT) From: Romain TISSERAND To: Chaoyi Chen Cc: Romain TISSERAND , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Heiko Stuebner , Liu Ying , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm/bridge: dw-mipi-dsi: use the lane rate for lbcc when lanes run faster Date: Fri, 30 Oct 2026 15:10:18 +0100 Message-ID: <20261030141018.3851266-1-romain.tisserand@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <9e3dc854-b2f5-459c-8267-55e88e87f5b5@rock-chips.com> References: <20261025142639.3454322-1-romain.tisserand@gmail.com> <9e3dc854-b2f5-459c-8267-55e88e87f5b5@rock-chips.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Chaoyi, On 10/26/2026 3:17 AM, Chaoyi Chen wrote: > Adding different glue code for each implementation seems like a good > idea. > > Maybe you should try to add a new callback in dw_mipi_dsi_plat_data ? Makes sense. For v2 I've dropped the threshold and added an optional get_hcomponent_lbcc() callback to dw_mipi_dsi_plat_data. The Rockchip glue implements it from its lane rate, and the other glues keep the current code since they don't set it. I've retested on the GPD XD and will send it on November 1st. Thanks, Romain