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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4aa813d2950sm145233925e9.8.2026.10.30.09.28.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 09:28:43 -0700 (PDT) Date: Fri, 30 Oct 2026 16:28:41 +0000 From: David Laight To: Steve Wahl Cc: Peter Zijlstra , Dave Hansen , "H. Peter Anvin" , x86@kernel.org, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, justin.ernst@hpe.com, kyle.meyer@hpe.com, dimitri.sivanich@hpe.com, russ.anderson@hpe.com, linux-kernel@vger.kernel.org, mhiramat@kernel.org, Matt Mullins Subject: Re: [PATCH] x86: Drop KGDB support Message-ID: <20261030162841.23ffeb6b@pumpkin> In-Reply-To: References: <20261028122124.GJ2668804@noisy.programming.kicks-ass.net> <28F95BAB-6D5B-4C70-A9F2-14B752EBF022@zytor.com> <20261028142625.GU2668564@noisy.programming.kicks-ass.net> <27a7b4b6-23da-4469-9161-2ce44e8ac2a9@intel.com> <20261029105121.39a4c74f@pumpkin> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 29 Oct 2026 10:32:58 -0500 Steve Wahl wrote: > On Thu, Oct 29, 2026 at 10:51:21AM +0000, David Laight wrote: > > On Wed, 28 Oct 2026 14:58:12 -0500 > > Steve Wahl wrote: > > > > > On Wed, Oct 28, 2026 at 08:10:54AM -0700, Dave Hansen wrote: > > ... > > > > > > For an example, I recently used this method to discover that at > > > least one version of Intel's MPI library likes to read up > > > /proc/kallsyms from each of the processes it starts, and somewhere > > > north of 1000's of processors the atomic increment on opening > > > kallsyms, implemented with a compare-exchange, becomes a hot lock > > > and initialization that takes little time on a smaller number of > > > processors, suddenly balloons to half an hour. > > > > I'm guessing that was pre-ARMv8.1 ?? > > x86, not arm. And it was on a distro kernel, I didn't check the > current community kernel because it was a situation where it was > enough to understand what's going on in the distro kernel, and avoid > the behavior in the application. x86 shouldn't have an exponential issue with cas. Something else must have been going on. David > > > The LL/SC retry loops for atomics are completely broken for contended > > operations. > > The kernel needs to patch them to use the LSE (single instruction > > atomics) for ARMv8.1 which guarantee that some progress is made. > > A CAS loop can still get starved on a single CPU, but some CPU > > do proceed. > > You really don't want to use LL/LC on a system with hraair CPU. > > > > One CPU (not arm) that implements LL/SC locks the cache line for a > > few clocks after LL to give a reasonable chance of the associated SC > > actually succeeding before the cache line is 'stolen' by another CPU > > doing an LL. > > Thanks, > > --> Steve >