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Signed-off-by: Besar Wicaksono --- .../arm64/nvidia/t410/uncore-pcie_tgt.json | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie_tgt.json diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie_tgt.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie_tgt.json new file mode 100644 index 000000000000..0f4765042d1f --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie_tgt.json @@ -0,0 +1,83 @@ +[ + { + "EventCode": "0x4", + "EventName": "PCIE_TGT_CYCLES", + "BriefDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.", + "PublicDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.", + "Unit": "nvidia_pcie_tgt_pmu_,rc_" + }, + { + "EventCode": "0x2", + "EventName": "PCIE_TGT_RD_REQ", + "BriefDescription": "Counts read requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex.", + "PublicDescription": "Counts read requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex, where the target responds with data. Request size can be from 1 to 256 bytes. Filters: dst_rp_mask selects PCIe BAR traffic to root ports (bit n = root port n). dst_addr_en with dst_addr_base and dst_addr_mask selects PCIe BAR or CXL HDM addresses that equal the base in the mask's set bits. If both dst_rp_mask and the address filter are set, a request matching either is counted. With no filter, PCIe BAR traffic to all root ports is counted.", + "Unit": "nvidia_pcie_tgt_pmu_,rc_" + }, + { + "EventCode": "0x3", + "EventName": "PCIE_TGT_WR_REQ", + "BriefDescription": "Counts write requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex.", + "PublicDescription": "Counts write requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex, where the source sends data. Request size can be from 1 to 256 bytes. Filters: dst_rp_mask selects PCIe BAR traffic to root ports (bit n = root port n). dst_addr_en with dst_addr_base and dst_addr_mask selects PCIe BAR or CXL HDM addresses that equal the base in the mask's set bits. If both dst_rp_mask and the address filter are set, a request matching either is counted. With no filter, PCIe BAR traffic to all root ports is counted.", + "Unit": "nvidia_pcie_tgt_pmu_,rc_" + }, + { + "EventCode": "0x0", + "EventName": "PCIE_TGT_RD_BYTES", + "BriefDescription": "Counts bytes transferred by the read requests counted by PCIE_TGT_RD_REQ.", + "PublicDescription": "Counts bytes transferred by the read requests counted by PCIE_TGT_RD_REQ. Destination filters work as described for PCIE_TGT_RD_REQ.", + "Unit": "nvidia_pcie_tgt_pmu_,rc_" + }, + { + "EventCode": "0x1", + "EventName": "PCIE_TGT_WR_BYTES", + "BriefDescription": "Counts bytes transferred by the write requests counted by PCIE_TGT_WR_REQ.", + "PublicDescription": "Counts bytes transferred by the write requests counted by PCIE_TGT_WR_REQ. Destination filters work as described for PCIE_TGT_WR_REQ.", + "Unit": "nvidia_pcie_tgt_pmu_,rc_" + }, + { + "MetricName": "pcie_tgt_freq", + "MetricGroup": "PCIE_TGT_Frequency", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(PCIE_TGT_CYCLES / aggr_nr(PCIE_TGT_CYCLES)) / 1e9 / duration_time", + "ScaleUnit": "1GHz", + "BriefDescription": "Frequency of the cycles at the PCIe interface to the Tegra SoC data fabric.", + "PublicDescription": "Average frequency of the cycles at the PCIe interface to the Tegra SoC data fabric over the measurement interval.", + "Unit": "nvidia_pcie_tgt_pmu_,rc_" + }, + { + "MetricName": "pcie_tgt_avg_rd_bandwidth_to_all_dst", + "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR_CXL_HDM", + "MetricExpr": "PCIE_TGT_RD_BYTES@dst_addr_en=1,dst_addr_base=0,dst_addr_mask=0@ / 1e6 / duration_time", + "ScaleUnit": "1MB/s", + "BriefDescription": "Average read bandwidth to all PCIe BAR and CXL HDM ranges under this PCIe root complex.", + "PublicDescription": "Average read bandwidth of requests from any source to all PCIe BAR and CXL HDM ranges under this PCIe root complex.", + "Unit": "nvidia_pcie_tgt_pmu_,rc_" + }, + { + "MetricName": "pcie_tgt_avg_wr_bandwidth_to_all_dst", + "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR_CXL_HDM", + "MetricExpr": "PCIE_TGT_WR_BYTES@dst_addr_en=1,dst_addr_base=0,dst_addr_mask=0@ / 1e6 / duration_time", + "ScaleUnit": "1MB/s", + "BriefDescription": "Average write bandwidth to all PCIe BAR and CXL HDM ranges under this PCIe root complex.", + "PublicDescription": "Average write bandwidth of requests from any source to all PCIe BAR and CXL HDM ranges under this PCIe root complex.", + "Unit": "nvidia_pcie_tgt_pmu_,rc_" + }, + { + "MetricName": "pcie_tgt_avg_rd_bandwidth_to_pcie_bar", + "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR", + "MetricExpr": "PCIE_TGT_RD_BYTES / 1e6 / duration_time", + "ScaleUnit": "1MB/s", + "BriefDescription": "Average read bandwidth of PCIe BAR traffic to all root ports under this PCIe root complex.", + "PublicDescription": "Average read bandwidth of PCIe BAR traffic from any source to all root ports under this PCIe root complex.", + "Unit": "nvidia_pcie_tgt_pmu_,rc_" + }, + { + "MetricName": "pcie_tgt_avg_wr_bandwidth_to_pcie_bar", + "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR", + "MetricExpr": "PCIE_TGT_WR_BYTES / 1e6 / duration_time", + "ScaleUnit": "1MB/s", + "BriefDescription": "Average write bandwidth of PCIe BAR traffic to all root ports under this PCIe root complex.", + "PublicDescription": "Average write bandwidth of PCIe BAR traffic from any source to all root ports under this PCIe root complex.", + "Unit": "nvidia_pcie_tgt_pmu_,rc_" + } +] -- 2.43.0