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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cdb0983427csm1171058a12.29.2026.10.30.14.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 14:19:50 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 09/19] drm/msm: Rename sysprof_setup() Date: Fri, 30 Oct 2026 14:18:11 -0700 Message-ID: <20261030211928.45761-10-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261030211928.45761-1-robin.clark@oss.qualcomm.com> References: <20261030211928.45761-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: ii_2peJv0bPfZjcWQdcJ5ib2MessF_4Q X-Authority-Analysis: v=2.4 cv=Z6N5j3RA c=1 sm=1 tr=0 ts=6ae509f8 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=MKlMNXPVnuVdJcRjF-wA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDMwMDA4NSBTYWx0ZWRfXyYHKgd7lYyKW 5QKBABrZKEViiN+ZmhCbBPQJFD8ZJmSBU8hK2Hcbid2x4bqmnNO/9yv4tGov8fsI2bEGkRxcWPD i0xr6x9ixjTsCsH9IR0EY88B25hjjsDZXfuJ0KlqWhpJ/9QNu+8J17QwyQug24qxCowQX2N7OrV CWKZuZRk8sKKHh5dp7RRLX+9ihZ6Tq81bQgIJCcyKTutJuX6ZYPwqpvpLnQs7WXn9YQIFKEMgjz cNwhHpVADeHxOcqa2DWVPzsQ5dQvSG2TAWTC84YDxtAvu33K9ICrbU5J921UzZWXi2OZBpJVcO6 ODWFiKdPorVi+v3DDh4ZiXCEty4mObCA8OLuPC4mLrEITmKBzGT82+7RJ3GQKKVaxto1kx1dAjm buTvDLDt+sQ3DBM5QlpMuqHKupfoCQF9tFUBn4bgqAz+vAsF7zFGt6sz5nZUwG6+bSJSUxmp18l Xmvx3jlB77J0FYex/aA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDMwMDA4NSBTYWx0ZWRfX7Kcue+up0vH5 6p921xyQq/sSLR6CdWKP16Z75HpvkCsOz8W/jmqOo9hhuFfRU/67l3D2W+u4b0vVFvxLIpFSV68 NRyVmqAbrwepAPbNIYuzjt/Fg9yA3/Q= X-Proofpoint-ORIG-GUID: ii_2peJv0bPfZjcWQdcJ5ib2MessF_4Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-30_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 adultscore=0 bulkscore=0 clxscore=1015 malwarescore=0 phishscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2610300085 We'll need this for other non-sysprof related things, so give it a better name. It keeps the behavior of implicit force_on when sysprof is active, to avoid accidentially re-enabling IFPC when sysprof is active. That isn't a problem yet (PERFCNTR_CONFIG is not intended to be used with SYSPROF), but it will be for future users. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 17 +++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 2 +- drivers/gpu/drm/msm/msm_perfcntr.c | 8 ++++---- drivers/gpu/drm/msm/msm_submitqueue.c | 4 ++-- 6 files changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 662f09bec9d5..f3ec78226ed3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2128,13 +2128,22 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, return irq; } -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on) +/** + * a6xx_gmu_ifpc_update - Update IFPC inhibit OOB request + * @gpu: the gpu device + * @force_on: whether to force GPU on (disable IFPC) + * + * Update IFPC OOB request, if force_on is true, set an OOB request to + * force the GPU on (disable IFPC), if false drop the OOB request. + */ +void a6xx_gmu_ifpc_update(struct msm_gpu *gpu, bool force_on) { - bool sysprof = msm_gpu_sysprof_no_ifpc(gpu) || force_on; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + force_on |= msm_gpu_sysprof_no_ifpc(gpu); + /* Nothing to do if GPU is suspended. We will handle this during GMU resume */ if (!pm_runtime_get_if_active(&gpu->pdev->dev)) return; @@ -2145,9 +2154,9 @@ void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on) * 'Perfcounter select' register values are lost during IFPC collapse. To avoid that, * use the currently unused perfcounter oob vote to block IFPC when sysprof is active */ - if (sysprof && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + if (force_on && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); - else if (!sysprof && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + else if (!force_on && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); mutex_unlock(&gmu->lock); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 09d76cdf059f..70c0024bdef4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2851,7 +2851,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a6xx_progress, - .sysprof_setup = a6xx_gmu_sysprof_setup, + .ifpc_update = a6xx_gmu_ifpc_update, .perfcntr_configure = a6xx_perfcntr_configure, }, .init = a6xx_gpu_init, @@ -2922,7 +2922,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a6xx_progress, - .sysprof_setup = a6xx_gmu_sysprof_setup, + .ifpc_update = a6xx_gmu_ifpc_update, .perfcntr_configure = a6xx_perfcntr_configure, }, .init = a6xx_gpu_init, @@ -2953,7 +2953,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a8xx_progress, - .sysprof_setup = a6xx_gmu_sysprof_setup, + .ifpc_update = a6xx_gmu_ifpc_update, .perfcntr_configure = a6xx_perfcntr_configure, .perfcntr_flush = a8xx_perfcntr_flush, }, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index c49301be504b..639e63c29f4b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -298,7 +298,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on); +void a6xx_gmu_ifpc_update(struct msm_gpu *gpu, bool force_on); void a6xx_preempt_init(struct msm_gpu *gpu); void a6xx_preempt_hw_init(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index d27d54bdb7a7..2e1b1bea37ce 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -93,7 +93,7 @@ struct msm_gpu_funcs { * for cmdstream that is buffered in this FIFO upstream of the CP fw. */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); - void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on); + void (*ifpc_update)(struct msm_gpu *gpu, bool force_on); /* Configure perfcntr SELect regs: */ void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring, diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_perfcntr.c index ce65b1160955..7b4a6e49d3a7 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.c +++ b/drivers/gpu/drm/msm/msm_perfcntr.c @@ -259,8 +259,8 @@ sample_worker(struct kthread_work *work) } /* Inhibit IFPC while accessing registers: */ - if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu, true); + if (gpu->funcs->ifpc_update) + gpu->funcs->ifpc_update(gpu, true); if (gpu->funcs->perfcntr_flush) gpu->funcs->perfcntr_flush(gpu); @@ -297,8 +297,8 @@ sample_worker(struct kthread_work *work) } /* Re-enable IFPC: */ - if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu, false); + if (gpu->funcs->ifpc_update) + gpu->funcs->ifpc_update(gpu, false); smp_store_release(&stream->fifo.head, head); wake_up_all(&stream->poll_wq); diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index d307cdd17d90..43103b054ee7 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -43,8 +43,8 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy } /* Some gpu families require additional setup for sysprof */ - if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu, false); + if (gpu->funcs->ifpc_update) + gpu->funcs->ifpc_update(gpu, false); ctx->sysprof = sysprof; -- 2.56.0