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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2eb3927e856sm11374025ad.50.2026.10.30.14.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 14:20:24 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 18/19] drm/msm/a8xx: Switch to generated protect regs Date: Fri, 30 Oct 2026 14:18:20 -0700 Message-ID: <20261030211928.45761-19-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261030211928.45761-1-robin.clark@oss.qualcomm.com> References: <20261030211928.45761-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 7WftvGF2HUGDSx3nEGBR5Ci1H76AfwWJ X-Proofpoint-ORIG-GUID: 7WftvGF2HUGDSx3nEGBR5Ci1H76AfwWJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDMwMDA4NSBTYWx0ZWRfX3nJUYOgpvNMs PUOQoKxQlsR2DkqN1p7TE3HiB9SS9j1ae6Ez83PYHBCwtLOwMr3VB23n/ZKqAD61AMPQNx8UGxr jkjaevcWCaqWby1WKNwKoH8fijXOhtlLogHZrhPJM0neAQHW7R7n7XOb52HzU5/LwPUSfAbWhSH cECd+M8Q1ZzgYAl5hj+WgNOSCreMMP7S7a365R+G6cwBagIcGt6Ed9uclXuzII6oi2px7wCGau7 7ge4MgvOs0IEDm/FjW6oXBHzPMZr9z5A+eU2jhi7JAUC9SYHF+kNhndHu8keVeGB5Q0zf+k2Kzy AuG3tdSvbPvWZxBcbtY1lcdE1X4snBjq4bVMNGDU4fe+Sjg5B0IUOhsY+P1P9lIfl5vdp50FJpp OlDbC2suIub1Efdf0zs/3ZEMfDzj4pRFsqTLDO3msELZwSZwyeiVw9zxkZM76NMgbBPOniBofOH E/AKAwA4dj4B/4MYetA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDMwMDA4NSBTYWx0ZWRfX+6iZt7TJkpwQ t6sNz9a9owAlVJzqeI3ZYmxNSbI7CVFXYK1B/oFp0kLGLBgR/qK6v/ji+sjRljIIRZOoqS3mgxS gWcOEJuBfBDLdHv9s4wqbDphIBEB5H4= X-Authority-Analysis: v=2.4 cv=ZOdCCn7b c=1 sm=1 tr=0 ts=6ae50a1a cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=JcQOObtfp6PrThPhMQoA:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-30_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 phishscore=0 malwarescore=0 impostorscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2610300085 These also fix some perfcntr SEL regs which were mistakenly blocked since we previously just copied the protect tables from downstream kgsl (and only sometimes remembered to fix these). Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_catalog.c | 301 +--------------------- 1 file changed, 13 insertions(+), 288 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c index 6fb35db73db3..dcb61bb09489 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c @@ -82,58 +82,6 @@ static const struct adreno_reglist_pipe a830_nonctxt_regs[] = { { }, }; -static const u32 a830_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x03a3), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0787), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x20000, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0381), - A6XX_PROTECT_NORDWR(0x27882, 0x0001), - A6XX_PROTECT_NORDWR(0x27c02, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a830_protect, 64); - static const u32 a830_pwrup_reglist_regs[] = { REG_A6XX_UCHE_MODE_CNTL, REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, @@ -364,63 +312,6 @@ static const struct adreno_reglist_pipe x285_nonctxt_regs[] = { { }, }; -static const u32 x285_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x0082c, 0x0000), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x000a), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; - -DECLARE_ADRENO_PROTECT(x285_protect, 15); - static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = { { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, @@ -522,57 +413,6 @@ static const struct adreno_reglist_pipe a810_nonctxt_regs[] = { { }, }; -static const u32 a810_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x03a3), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0787), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x20000, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0381), - A6XX_PROTECT_NORDWR(0x27882, 0x0001), - A6XX_PROTECT_NORDWR(0x27c02, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a810_protect, 64); - static const uint32_t a810_pwrup_reglist_regs[] = { REG_A6XX_UCHE_MODE_CNTL, REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, @@ -889,64 +729,6 @@ static const struct adreno_reglist_pipe a840_nonctxt_regs[] = { { }, }; -static const u32 a840_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x001b), - A6XX_PROTECT_NORDWR(0x00775, 0x000a), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_NORDWR(0x00c07, 0x0008), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x0009), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a840_protect, 15); - static const struct adreno_reglist a840_gbif[] = { { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 }, { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 }, @@ -1350,67 +1132,6 @@ static const struct adreno_reglist_pipe a850_nonctxt_regs[] = { { }, }; -static const u32 a850_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x001b), - A6XX_PROTECT_NORDWR(0x00775, 0x000a), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_NORDWR(0x00c07, 0x0008), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00df5, 0x0003), - A6XX_PROTECT_RDONLY(0x00df9, 0x0007), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1ac00, 0x1fff), - A6XX_PROTECT_NORDWR(0x1cc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x0035), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a850_protect, 15); - static const u32 a850_pwrup_reglist_regs[] = { REG_A8XX_RB_CMP_NC_MODE_CNTL, REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, @@ -1631,7 +1352,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a830_protect, + .protect = &pakala_protect, .nonctxt_reglist = a830_nonctxt_regs, .pwrup_reglist = &a830_pwrup_reglist, .dyn_pwrup_reglist = &a830_dyn_pwrup_reglist, @@ -1676,7 +1397,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_SOFTFUSE, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &x285_protect, + .protect = &glymur_protect, .nonctxt_reglist = x285_nonctxt_regs, .pwrup_reglist = &a840_pwrup_reglist, .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist, @@ -1721,7 +1442,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a840_protect, + .protect = &kaanapali_protect, .nonctxt_reglist = a840_nonctxt_regs, .pwrup_reglist = &a840_pwrup_reglist, .dyn_pwrup_reglist = &a840_dyn_pwrup_reglist, @@ -1767,7 +1488,7 @@ static const struct adreno_info a8xx_gpus[] = { .funcs = &a8xx_gpu_funcs, .zapfw = "gen80300_zap.mbn", .a6xx = &(const struct a6xx_info) { - .protect = &a810_protect, + .protect = &milos_protect, .nonctxt_reglist = a810_nonctxt_regs, .pwrup_reglist = &a810_pwrup_reglist, .dyn_pwrup_reglist = &a810_dyn_pwrup_reglist, @@ -1810,7 +1531,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_SOFTFUSE, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &x285_protect, + .protect = &glymur_protect, .nonctxt_reglist = x285_nonctxt_regs, .pwrup_reglist = &a840_pwrup_reglist, .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist, @@ -1853,7 +1574,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a850_protect, + .protect = &maili_protect, .nonctxt_reglist = a845_nonctxt_regs, .pwrup_reglist = &a850_pwrup_reglist, .dyn_pwrup_reglist = &a850_dyn_pwrup_reglist, @@ -1897,7 +1618,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a850_protect, + .protect = &hawi_protect, .nonctxt_reglist = a850_nonctxt_regs, .pwrup_reglist = &a850_pwrup_reglist, .dyn_pwrup_reglist = &a850_dyn_pwrup_reglist, @@ -1932,6 +1653,10 @@ DECLARE_ADRENO_GPULIST(a8xx); static inline __always_unused void __build_asserts(void) { - BUILD_BUG_ON(a810_protect.count > a810_protect.count_max); - BUILD_BUG_ON(a830_protect.count > a830_protect.count_max); + BUILD_BUG_ON(glymur_protect.count > glymur_protect.count_max); + BUILD_BUG_ON(hawi_protect.count > hawi_protect.count_max); + BUILD_BUG_ON(kaanapali_protect.count > kaanapali_protect.count_max); + BUILD_BUG_ON(maili_protect.count > maili_protect.count_max); + BUILD_BUG_ON(milos_protect.count > milos_protect.count_max); + BUILD_BUG_ON(pakala_protect.count > pakala_protect.count_max); } -- 2.56.0