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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2eb392aa7absm11605155ad.65.2026.10.30.14.19.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 14:19:40 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 03/19] drm/msm/a8xx: Add a8xx_aperture_acquire_raw() Date: Fri, 30 Oct 2026 14:18:05 -0700 Message-ID: <20261030211928.45761-4-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261030211928.45761-1-robin.clark@oss.qualcomm.com> References: <20261030211928.45761-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDMwMDA4NCBTYWx0ZWRfX5DGcUxqbg1Va Cq6YMPHEj/qnSyre714kftUE9ByCYmeAq04gz8GRPNdoqABfpZQvdDllCvlXte9qscfgq0DieqX NMHGErZt8l8C7lAlFbaklicdG5kE9tE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDMwMDA4NCBTYWx0ZWRfX5gxC94nV4Td4 NI1Xsfsoz1ZZOcJa9CPKtXjkpKQcxhO3GmR/WBekE7U5QP8WC7LIqP6G4kcchiv6voZJAKrcy4f A6DdiSjwz9yqSBBhZmW3zTA5pmy9rBxym6KHmDXXdvWO9+E9FXQym14bspDv9V4zCZHVYaIPJWm fcwyGcXDpDcbG+1vipa/MIcXK89m2KG+/JiSqWewP7/OD/VKmH1+84L3xbRnTQWJ6lYP7aTp6ms GzDaYqmqwba+2bID1byHeYVTWQaxx4jkoSHOkLbf/3daonMwE7FyzjMikv84fIOlNSpsuz9eXK2 PwMbD5iPsXa18dMzxOkP9YdIyQcQNNt3zGWup8VPbHgmmT1c/FlQ5E3nYswa8Q3+PVVU8yQ2bsE c8qxp25H06Rgoo2DcWgVoHp7Ksf4Sw== X-Proofpoint-GUID: UQVPv-z6B-lS_LQZQmMIE6_-E3JQgwfT X-Authority-Analysis: v=2.4 cv=FcSiV5+6 c=1 sm=1 tr=0 ts=6ae509ee cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=qGl0e74_xy6xiHm5yPkA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: UQVPv-z6B-lS_LQZQmMIE6_-E3JQgwfT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-30_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2610300084 The snapshot code will need more control, setting additional bitfields. Rather than add a list of additional args, add a helper to acquire the aperture which directly takes a reg value. Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 21 +++++++++++++-------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index fb000b79fe2f..2a2ddba6761f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -348,6 +348,7 @@ void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); void a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring); int a6xx_zap_shader_init(struct msm_gpu *gpu); +void a8xx_aperture_acquire_raw(struct msm_gpu *gpu, u32 val, unsigned long *flags); void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags); void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags); void a8xx_aperture_clear(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index a14379e26fbe..a0983e2ee641 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -16,13 +16,10 @@ #define GPU_PAS_ID 13 -static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) +static void a8xx_aperture_slice_set(struct msm_gpu *gpu, u32 val) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - u32 val; - - val = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice); if (a6xx_gpu->cached_aperture == val) return; @@ -32,14 +29,20 @@ static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, a6xx_gpu->cached_aperture = val; } -void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) +void a8xx_aperture_acquire_raw(struct msm_gpu *gpu, u32 val, unsigned long *flags) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags); - a8xx_aperture_slice_set(gpu, pipe, 0); + a8xx_aperture_slice_set(gpu, val); + +} + +void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) +{ + a8xx_aperture_acquire_raw(gpu, A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe), flags); } void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) @@ -74,8 +77,10 @@ static u32 a8xx_read_pipe_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 unsigned long flags; u32 val; - spin_lock_irqsave(&a6xx_gpu->aperture_lock, flags); - a8xx_aperture_slice_set(gpu, pipe, slice); + a8xx_aperture_acquire_raw(gpu, + A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | + A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice), + &flags); val = gpu_read(gpu, offset); spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags); -- 2.56.0