From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Paul Elder <paul.elder+renesas@ideasonboard.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Magnus Damm <magnus.damm@gmail.com>,
Ulf Hansson <ulfh@kernel.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-pm@vger.kernel.org, linux-media@vger.kernel.org
Subject: Re: [PATCH DNI v3 06/15] arm64: renesas: r8a78000: Add FCPVD and VSPD nodes
Date: Fri, 30 Oct 2026 23:42:32 +0200 [thread overview]
Message-ID: <20261030214232.GD3178046@killaraus.ideasonboard.com> (raw)
In-Reply-To: <20261015-epaul-v7-3-rc1-x5h-vsp-fcp-v3-6-e052903a3832@ideasonboard.com>
On Thu, Oct 15, 2026 at 04:51:46PM +0900, Paul Elder wrote:
> Add DT nodes for the FCPVD and VSPD IP cores in the R-Car X5H SoC.
>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>
> ---
> Changes in v3:
> - Fix the mapping between VSPD and FCPVD nodes so that they all work
That was a good catch. I think the weird mapping comes from how the VSPD
instances are connected to VCON groups:
- VCON group 0 (VCON[0123], DPTX0): VSPDa0, VSPDa1, VSPDb0, VSPDb1
- VCON group 1 (VCON[4567], DPTX1): VSPDa2, VSPDa3, VSPDb2, VSPDb3
- VCON group 2 (VCON[89], DPTX2): VSPDa4, VSPDb4
> ---
> arch/arm64/boot/dts/renesas/r8a78000.dtsi | 190 ++++++++++++++++++++++++++++++
> 1 file changed, 190 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index f90b869579d384e3fc13d0a13625b7cddaac2868..1fa4896739110de1e445bfcd631d4937bda40714 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -1000,6 +1000,196 @@ mdlc_aon: system-controller@c1338000 {
> bootph-all;
> };
>
> + fcpvd0: fcp@c5010000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xc5010000 0 0x1000>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
Here (and below) too I would use SGD1.
> + power-domains = <&mdlc_vio 0x07 0x7e>;
> + resets = <&mdlc_vio 0x7e>;
> + };
> +
> + fcpvd1: fcp@c5011000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xc5011000 0 0x1000>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x7f>;
> + resets = <&mdlc_vio 0x7f>;
> + };
> +
> + fcpvd2: fcp@c5012000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xc5012000 0 0x1000>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x80>;
> + resets = <&mdlc_vio 0x80>;
> + };
> +
> + fcpvd3: fcp@c5013000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xc5013000 0 0x1000>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x81>;
> + resets = <&mdlc_vio 0x81>;
> + };
> +
> + fcpvd4: fcp@c5014000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xc5014000 0 0x1000>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x82>;
> + resets = <&mdlc_vio 0x82>;
> + };
> +
> + fcpvd5: fcp@c5015000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xc5015000 0 0x1000>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x83>;
> + resets = <&mdlc_vio 0x83>;
> + };
> +
> + fcpvd6: fcp@c5016000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xc5016000 0 0x1000>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x84>;
> + resets = <&mdlc_vio 0x84>;
> + };
> +
> + fcpvd7: fcp@c5017000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xc5017000 0 0x1000>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x85>;
> + resets = <&mdlc_vio 0x85>;
> + };
> +
> + fcpvd8: fcp@c5018000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xc5018000 0 0x1000>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x86>;
> + resets = <&mdlc_vio 0x86>;
> + };
> +
> + fcpvd9: fcp@c5019000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xc5019000 0 0x1000>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x87>;
> + resets = <&mdlc_vio 0x87>;
> + };
> +
> + vspd0: vsp@c4800000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc4800000 0 0x8000>;
> + interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x70>;
> + resets = <&mdlc_vio 0x70>;
> +
> + renesas,fcp = <&fcpvd0>;
> + };
> +
> + vspd1: vsp@c4808000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc4808000 0 0x8000>;
> + interrupts = <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x71>;
> + resets = <&mdlc_vio 0x71>;
> +
> + renesas,fcp = <&fcpvd1>;
> + };
> +
> + vspd2: vsp@c4810000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc4810000 0 0x8000>;
> + interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x72>;
> + resets = <&mdlc_vio 0x72>;
> +
> + renesas,fcp = <&fcpvd4>;
> + };
> +
> + vspd3: vsp@c4818000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc4818000 0 0x8000>;
> + interrupts = <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x73>;
> + resets = <&mdlc_vio 0x73>;
> +
> + renesas,fcp = <&fcpvd5>;
> + };
> +
> + vspd4: vsp@c4820000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc4820000 0 0x8000>;
> + interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x74>;
> + resets = <&mdlc_vio 0x74>;
> +
> + renesas,fcp = <&fcpvd8>;
> + };
> +
> + vspdb0: vsp@c4828000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc4828000 0 0x8000>;
> + interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x75>;
> + resets = <&mdlc_vio 0x75>;
> +
> + renesas,fcp = <&fcpvd2>;
> + };
> +
> + vspdb1: vsp@c4830000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc4830000 0 0x8000>;
> + interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x76>;
> + resets = <&mdlc_vio 0x76>;
> +
> + renesas,fcp = <&fcpvd3>;
> + };
> +
> + vspdb2: vsp@c4838000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc4838000 0 0x8000>;
> + interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x77>;
> + resets = <&mdlc_vio 0x77>;
> +
> + renesas,fcp = <&fcpvd6>;
> + };
> +
> + vspdb3: vsp@c4840000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc4840000 0 0x8000>;
> + interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x78>;
> + resets = <&mdlc_vio 0x78>;
> +
> + renesas,fcp = <&fcpvd7>;
> + };
> +
> + vspdb4: vsp@c4848000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc4848000 0 0x8000>;
> + interrupts = <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> + power-domains = <&mdlc_vio 0x07 0x79>;
> + resets = <&mdlc_vio 0x79>;
> +
> + renesas,fcp = <&fcpvd9>;
> + };
> +
> fcpvi0: fcp@c5030000 {
> compatible = "renesas,fcpv";
> reg = <0 0xc5030000 0 0x1000>;
>
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2026-10-30 21:42 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-15 7:51 [PATCH DNI v3 00/15] media: rcar-fcp, vsp1: Enable on R-Car X5H Paul Elder
2026-10-15 7:51 ` [PATCH DNI v3 01/15] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER} Paul Elder
2026-10-30 21:57 ` Laurent Pinchart
2026-10-15 7:51 ` [PATCH DNI v3 02/15] clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36 Paul Elder
2026-10-15 7:51 ` [PATCH DNI v3 03/15] pmdomain: renesas: r8a78000: Add maps for VIO " Paul Elder
2026-10-30 22:05 ` Laurent Pinchart
2026-10-15 7:51 ` [PATCH DNI v3 04/15] arm64: renesas: r8a78000: Add FCPV[BI] nodes Paul Elder
2026-10-30 21:12 ` Laurent Pinchart
2026-10-15 7:51 ` [PATCH DNI v3 05/15] arm64: renesas: r8a78000: Add VSP[BI] nodes Paul Elder
2026-10-30 21:38 ` Laurent Pinchart
2026-10-15 7:51 ` [PATCH DNI v3 06/15] arm64: renesas: r8a78000: Add FCPVD and VSPD nodes Paul Elder
2026-10-30 21:42 ` Laurent Pinchart [this message]
2026-10-15 7:51 ` [PATCH v3 07/15] media: vsp1: Support full VSPB on R-Car M3-W, M3-N and E3 Paul Elder
2026-10-15 7:51 ` [PATCH v3 08/15] media: vsp1: Add device info entries for VSPD on X5H Paul Elder
2026-10-15 7:51 ` [PATCH v3 09/15] media: rcar-fcp: Handle resets Paul Elder
2026-10-15 7:51 ` [PATCH v3 10/15] media: vsp1: Fix access to reserved registers Paul Elder
2026-10-30 21:34 ` Laurent Pinchart
2026-10-15 7:51 ` [PATCH v3 11/15] media: vsp1: Fix du_complete race condition issue Paul Elder
2026-10-15 7:51 ` [PATCH v3 12/15] media: vsp1: Fix setting control register by display list Paul Elder
2026-10-30 21:51 ` Laurent Pinchart
2026-10-15 7:51 ` [PATCH v3 13/15] dt-bindings: Increase Renesas X5H MDLC PD specifier bit width Paul Elder
2026-10-17 16:36 ` Krzysztof Kozlowski
2026-10-30 21:28 ` Laurent Pinchart
2026-10-15 7:51 ` [PATCH v3 14/15] media: vsp1: Complete buffers as queued in start_streaming error path Paul Elder
2026-10-30 21:53 ` Laurent Pinchart
2026-10-15 7:51 ` [PATCH DNI v3 15/15] media: rcar-fcp: Check device revision at probe time Paul Elder
2026-10-20 12:20 ` Geert Uytterhoeven
2026-10-30 22:02 ` Laurent Pinchart
2026-10-20 13:22 ` Geert Uytterhoeven
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