From: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>,
Daniel Lezcano <daniel.lezcano@kernel.org>,
Zhang Rui <rui.zhang@intel.com>,
Lukasz Luba <lukasz.luba@arm.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Randy Dunlap <rdunlap@infradead.org>,
Amit Kucheria <amitk@kernel.org>,
Thara Gopinath <thara.gopinath@gmail.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Abel Vesa <abelvesa@kernel.org>
Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>,
Amit Kucheria <amit.kucheria@oss.qualcomm.com>
Subject: [PATCH v2 5/6] arm64: dts: qcom: kodiak: use thermal hw-bin trips
Date: Sat, 31 Oct 2026 18:52:51 +0530 [thread overview]
Message-ID: <20261031-thermal_bin-v2-5-d76fd073ae98@oss.qualcomm.com> (raw)
In-Reply-To: <20261031-thermal_bin-v2-0-d76fd073ae98@oss.qualcomm.com>
From: Amit Kucheria <amit.kucheria@oss.qualcomm.com>
kodiak-based SoCs are binned at manufacturing time, with the bin
computed from the jtag-id and feat-id qfprom fuses. The tsens driver
now reads these and feeds the resulting bin to the thermal core, which
selects per-bin trip temperatures.
Add the jtag-id and feat-id nvmem cells to the tsens nodes and convert
the passive mitigation trip points from a fixed 95C to per-bin values
(95C for bin 0x1, 105C for bin 0x2) using the new
temperature-bin/thermal-hw-bin properties.
Signed-off-by: Amit Kucheria <amit.kucheria@oss.qualcomm.com>
Co-developed-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 58 +++++++++++++++++++++++++++---------
1 file changed, 44 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 347815e5983e..b984cf47b70e 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -1019,6 +1019,18 @@ gpu_speed_bin: gpu-speed-bin@1e9 {
reg = <0x1e9 0x2>;
bits = <5 8>;
};
+
+ jtag_id: jtag-id@180 {
+ reg = <0x180 0x4>;
+ /* bits = <offset width>: 20 bits at offset 0 */
+ bits = <0 20>;
+ };
+
+ feat_id: feat-id@180 {
+ reg = <0x180 0x4>;
+ /* bits = <offset width>: 8 bits at offset 20 */
+ bits = <20 8>;
+ };
};
sdhc_1: mmc@7c4000 {
@@ -5782,6 +5794,8 @@ tsens0: thermal-sensor@c263000 {
compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
+ nvmem-cells = <&jtag_id>, <&feat_id>;
+ nvmem-cell-names = "jtag-id", "feat-id";
#qcom,sensors = <15>;
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
@@ -5793,6 +5807,8 @@ tsens1: thermal-sensor@c265000 {
compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
+ nvmem-cells = <&jtag_id>, <&feat_id>;
+ nvmem-cell-names = "jtag-id", "feat-id";
#qcom,sensors = <12>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
@@ -7136,7 +7152,8 @@ cpu0_alert0: trip-point0 {
};
cpu0_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7179,7 +7196,8 @@ cpu1_alert0: trip-point0 {
};
cpu1_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7222,7 +7240,8 @@ cpu2_alert0: trip-point0 {
};
cpu2_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7265,7 +7284,8 @@ cpu3_alert0: trip-point0 {
};
cpu3_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7308,7 +7328,8 @@ cpu4_alert0: trip-point0 {
};
cpu4_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7351,7 +7372,8 @@ cpu5_alert0: trip-point0 {
};
cpu5_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7394,7 +7416,8 @@ cpu6_alert0: trip-point0 {
};
cpu6_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7437,7 +7460,8 @@ cpu7_alert0: trip-point0 {
};
cpu7_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7480,7 +7504,8 @@ cpu8_alert0: trip-point0 {
};
cpu8_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7523,7 +7548,8 @@ cpu9_alert0: trip-point0 {
};
cpu9_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7566,7 +7592,8 @@ cpu10_alert0: trip-point0 {
};
cpu10_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7609,7 +7636,8 @@ cpu11_alert0: trip-point0 {
};
cpu11_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7724,7 +7752,8 @@ gpuss0-thermal {
trips {
gpuss0_alert0: trip-point0 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7751,7 +7780,8 @@ gpuss1-thermal {
trips {
gpuss1_alert0: trip-point0 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
--
2.34.1
next prev parent reply other threads:[~2026-10-31 13:23 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-31 13:22 [PATCH v2 0/6] thermal: Add hardware-binned trip point support Gaurav Kohli
2026-10-31 13:22 ` [PATCH v2 1/6] dt-bindings: thermal: thermal-zones: add hardware-binning trip properties Gaurav Kohli
2026-10-31 13:22 ` [PATCH v2 2/6] thermal: add hardware-binning trip-point filtering support Gaurav Kohli
2026-10-31 13:22 ` [PATCH v2 3/6] dt-bindings: thermal: qcom-tsens: document qcm6490 tsens Gaurav Kohli
2026-10-31 13:22 ` [PATCH v2 4/6] thermal: qcom: tsens: add hardware-bin trip-point filtering Gaurav Kohli
2026-10-31 13:22 ` Gaurav Kohli [this message]
2026-10-31 13:22 ` [PATCH v2 6/6] arm64: dts: qcom: hamoa: add thermal hw-bin support Gaurav Kohli
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