From: Enzo Adriano <enzo.adriano.code@gmail.com>
To: Andre Przywara <andre.przywara@arm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Chen-Yu Tsai <wens@kernel.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>
Cc: Maxime Ripard <mripard@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
Junhui Liu <junhui.liu@pigmoral.tech>,
Jerome Brunet <jbrunet@baylibre.com>,
Pablo Mazzini <pmazzini@gmail.com>,
Vinicius Pedrosa <vinicius.eduardo.pedrosa@gmail.com>
Subject: [PATCH v2 2/3] arm64: dts: allwinner: add A733 SoC description
Date: Fri, 30 Oct 2026 22:26:54 -0400 [thread overview]
Message-ID: <20261031020640-263f7b05-a7s-dt-v2-2@gmail.com> (raw)
In-Reply-To: <20261031020640-263f7b05-a7s-dt-v2-0@gmail.com>
Describe the CPUs, PSCI, architectural timers, GIC, RTC, main and
always-on clock/reset and pin controllers. Include all main and R-domain
UART/I2C instances and all four MMC controllers with their documented
pin groups.
MMC0/1/2 use the existing A733/D1 binding. MMC3 uses the distinct eMMC
binding because its DMA descriptors differ; it remains disabled. Add the
GIC maintenance PPI 9 and ARMv8.2 EL2 virtual-timer PPI 12. The
GICD/GICR/ITS windows and noncoherent attributes agree with Andre
Przywara's public A733 reference and the A523 integration precedent. The
manual's CPUX interconnect diagram supports noncoherency as an
integration inference. The ITS stays disabled until its clock/reset and
MSI path are integrated.
AI assistance: Codex:gpt-6-astra.
Assisted-by: LLM
Signed-off-by: Enzo Adriano <enzo.adriano.code@gmail.com>
---
.../arm64/boot/dts/allwinner/sun60i-a733.dtsi | 624 ++++++++++++++++++
1 file changed, 624 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi b/arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..522eda3d5dc9c7824dac41017162548e7a39d0a2
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+
+#include <dt-bindings/clock/sun6i-rtc.h>
+#include <dt-bindings/clock/allwinner,sun60i-a733-ccu.h>
+#include <dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/allwinner,sun60i-a733-ccu.h>
+#include <dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ reg = <0x200>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@300 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ reg = <0x300>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@400 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ reg = <0x400>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@500 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ reg = <0x500>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@600 {
+ compatible = "arm,cortex-a76";
+ device_type = "cpu";
+ reg = <0x600>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@700 {
+ compatible = "arm,cortex-a76";
+ device_type = "cpu";
+ reg = <0x700>;
+ enable-method = "psci";
+ };
+ };
+
+ osc: osc-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ arm,no-tick-in-suspend;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x40000000>;
+
+ pio: pinctrl@2000000 {
+ compatible = "allwinner,sun60i-a733-pinctrl";
+ reg = <0x02000000 0x800>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1>, <&osc>, <&rtc CLK_OSC32K>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+ function = "mmc0";
+ allwinner,pinmux = <2>;
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
+ function = "mmc1";
+ allwinner,pinmux = <2>;
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_pins: mmc2-pins {
+ pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11",
+ "PC13", "PC14", "PC15", "PC16";
+ function = "mmc2";
+ allwinner,pinmux = <3>;
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc3_pins: mmc3-pins {
+ pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11",
+ "PC13", "PC14", "PC15", "PC16";
+ function = "mmc3";
+ allwinner,pinmux = <4>;
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ uart0_pb_pins: uart0-pb-pins {
+ pins = "PB9", "PB10";
+ function = "uart0";
+ allwinner,pinmux = <2>;
+ };
+ };
+
+ ccu: clock-controller@2002000 {
+ compatible = "allwinner,sun60i-a733-ccu";
+ reg = <0x02002000 0x2000>;
+ clocks = <&osc>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
+ <&rtc CLK_OSC32K_FANOUT>;
+ clock-names = "hosc", "losc", "iosc", "losc-fanout";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ uart0: serial@2500000 {
+ compatible = "allwinner,sun60i-a733-uart",
+ "snps,dw-apb-uart";
+ reg = <0x02500000 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial@2501000 {
+ compatible = "allwinner,sun60i-a733-uart",
+ "snps,dw-apb-uart";
+ reg = <0x02501000 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial@2502000 {
+ compatible = "allwinner,sun60i-a733-uart",
+ "snps,dw-apb-uart";
+ reg = <0x02502000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@2503000 {
+ compatible = "allwinner,sun60i-a733-uart",
+ "snps,dw-apb-uart";
+ reg = <0x02503000 0x400>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ status = "disabled";
+ };
+
+ uart4: serial@2504000 {
+ compatible = "allwinner,sun60i-a733-uart",
+ "snps,dw-apb-uart";
+ reg = <0x02504000 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
+ status = "disabled";
+ };
+
+ uart5: serial@2505000 {
+ compatible = "allwinner,sun60i-a733-uart",
+ "snps,dw-apb-uart";
+ reg = <0x02505000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART5>;
+ resets = <&ccu RST_BUS_UART5>;
+ status = "disabled";
+ };
+
+ uart6: serial@2506000 {
+ compatible = "allwinner,sun60i-a733-uart",
+ "snps,dw-apb-uart";
+ reg = <0x02506000 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART6>;
+ resets = <&ccu RST_BUS_UART6>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2510000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x02510000 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2511000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x02511000 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2512000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x02512000 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2513000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x02513000 0x400>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@2514000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x02514000 0x400>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C4>;
+ resets = <&ccu RST_BUS_I2C4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@2515000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x02515000 0x400>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C5>;
+ resets = <&ccu RST_BUS_I2C5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@2516000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x02516000 0x400>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C6>;
+ resets = <&ccu RST_BUS_I2C6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@2517000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x02517000 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C7>;
+ resets = <&ccu RST_BUS_I2C7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@2518000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x02518000 0x400>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C8>;
+ resets = <&ccu RST_BUS_I2C8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@2519000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x02519000 0x400>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C9>;
+ resets = <&ccu RST_BUS_I2C9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@251a000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x0251a000 0x400>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C10>;
+ resets = <&ccu RST_BUS_I2C10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@251b000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x0251b000 0x400>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C11>;
+ resets = <&ccu RST_BUS_I2C11>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c12: i2c@251c000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x0251c000 0x400>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C12>;
+ resets = <&ccu RST_BUS_I2C12>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@3400000 {
+ compatible = "arm,gic-v3";
+ reg = <0x03400000 0x10000>, <0x03460000 0x100000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ dma-noncoherent;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ its: msi-controller@3440000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x03440000 0x20000>;
+ msi-controller;
+ #msi-cells = <1>;
+ dma-noncoherent;
+ status = "disabled";
+ };
+ };
+
+ mmc0: mmc@4020000 {
+ compatible = "allwinner,sun60i-a733-mmc",
+ "allwinner,sun20i-d1-mmc";
+ reg = <0x04020000 0x1000>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun60i-a733-mmc",
+ "allwinner,sun20i-d1-mmc";
+ reg = <0x04021000 0x1000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@4022000 {
+ compatible = "allwinner,sun60i-a733-mmc",
+ "allwinner,sun20i-d1-mmc";
+ reg = <0x04022000 0x1000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mmc3: mmc@4023000 {
+ compatible = "allwinner,sun60i-a733-emmc";
+ reg = <0x04023000 0x1000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>,
+ <&ccu CLK_MBUS_STORE>, <&ccu CLK_BUS_MSI_LITE1>;
+ clock-names = "ahb", "mmc", "mbus", "msi";
+ resets = <&ccu RST_BUS_MMC3>;
+ reset-names = "ahb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins>;
+ status = "disabled";
+ };
+
+ r_ccu: clock-controller@7010000 {
+ compatible = "allwinner,sun60i-a733-r-ccu";
+ reg = <0x07010000 0x250>;
+ clocks = <&osc>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
+ <&ccu CLK_SYS_24M>, <&ccu CLK_PLL_PERIPH0_200M>,
+ <&ccu CLK_PLL_PERIPH0_300M>,
+ <&ccu CLK_PLL_PERIPH1_300M>;
+ clock-names = "hosc", "losc", "iosc", "sys-24m",
+ "pll-periph0-200m", "pll-periph0-300m",
+ "pll-periph1-300m";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ nmi_intc: interrupt-controller@7010320 {
+ compatible = "allwinner,sun60i-a733-nmi",
+ "allwinner,sun55i-a523-nmi";
+ reg = <0x07010320 0xc>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ r_pio: pinctrl@7025000 {
+ compatible = "allwinner,sun60i-a733-r-pinctrl";
+ reg = <0x07025000 0x800>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB0>, <&osc>, <&rtc CLK_OSC32K>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ r_i2c0_pl_pins: r-i2c0-pl-pins {
+ pins = "PL0", "PL1";
+ function = "r_i2c0";
+ allwinner,pinmux = <2>;
+ };
+ };
+
+ r_uart0: serial@7080000 {
+ compatible = "allwinner,sun60i-a733-uart",
+ "snps,dw-apb-uart";
+ reg = <0x07080000 0x400>;
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&r_ccu CLK_BUS_R_UART0>;
+ resets = <&r_ccu RST_BUS_R_UART0>;
+ status = "disabled";
+ };
+
+ r_uart1: serial@7081000 {
+ compatible = "allwinner,sun60i-a733-uart",
+ "snps,dw-apb-uart";
+ reg = <0x07081000 0x400>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&r_ccu CLK_BUS_R_UART1>;
+ resets = <&r_ccu RST_BUS_R_UART1>;
+ status = "disabled";
+ };
+
+ r_i2c0: i2c@7083000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x07083000 0x400>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_BUS_R_I2C0>;
+ resets = <&r_ccu RST_BUS_R_I2C0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ r_i2c1: i2c@7084000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x07084000 0x400>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_BUS_R_I2C1>;
+ resets = <&r_ccu RST_BUS_R_I2C1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ r_i2c2: i2c@7085000 {
+ compatible = "allwinner,sun60i-a733-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x07085000 0x400>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_BUS_R_I2C2>;
+ resets = <&r_ccu RST_BUS_R_I2C2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rtc: rtc@7090000 {
+ compatible = "allwinner,sun60i-a733-rtc",
+ "allwinner,sun50i-r329-rtc";
+ reg = <0x07090000 0x400>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_BUS_R_RTC>, <&osc>, <&r_ccu CLK_R_AHB>;
+ clock-names = "bus", "hosc", "ahb";
+ #clock-cells = <1>;
+ };
+ };
+};
--
2.53.0
next prev parent reply other threads:[~2026-10-31 2:26 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-31 2:26 [PATCH v2 0/3] arm64: dts: allwinner: add A733/Cubie A7S support Enzo Adriano
2026-10-31 2:26 ` [PATCH v2 1/3] dt-bindings: arm: sunxi: document Radxa Cubie A7S Enzo Adriano
2026-10-31 2:26 ` Enzo Adriano [this message]
2026-10-31 2:26 ` [PATCH v2 3/3] arm64: dts: allwinner: add Radxa Cubie A7S board Enzo Adriano
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