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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-714f2e500d0sm3126067eaf.10.2026.10.30.19.26.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 19:26:49 -0700 (PDT) From: Enzo Adriano To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Maxime Ripard , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Junhui Liu Subject: [PATCH] dt-bindings: mmc: describe the Allwinner A733 eMMC controller Date: Fri, 30 Oct 2026 22:26:47 -0400 Message-ID: <20261031020640-263f7b05-a7s-mmc-binding@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit SMHC3 uses a different DMA descriptor format from SMHC0/2: the length field is 12 bits and the ownership/control word carries different control and high-address fields. An older A100/D1 fallback would claim unsupported programming compatibility with the existing sunxi-mmc descriptor builder. Give SMHC3 a distinct compatible and describe its register range, interrupt, bus/module/storage-MBUS/MSI-Lite1 clocks and bus reset. This binding permits an accurate disabled hardware description; no operational driver match or eMMC functionality is claimed here. AI assistance: Codex:gpt-6-astra. Assisted-by: LLM Signed-off-by: Enzo Adriano --- This binding is a separate prerequisite for the disabled MMC3 node in the A733 DT v2. It does not add a sunxi-mmc driver match or claim an operational eMMC path. The original A733 manual and public vendor implementation distinguish SMHC3's descriptor control/high-address fields and 12-bit buffer length from SMHC0-2. Its resources are the 0x04023000/0x1000 register window, SPI 164, AHB/module/storage-MBUS/MSI-Lite1 clocks and AHB reset. The generic A733/D1 MMC0-2 compatible already in the base is unchanged. The example uses the public A733 CCU header IDs. The tested standalone base is official commit d89e1d186ec9271bf78e62771779e9fc03bf0fc3 plus the clock helpers and CCU v6: https://lore.kernel.org/r/20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech https://lore.kernel.org/r/20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech The binding example passes dt_binding_check, and its disabled DTS user passes W=2 CHECK_DTBS=y. MMC0 runtime tests exercise the existing controller driver; they are not MMC3 hardware validation. .../mmc/allwinner,sun60i-a733-emmc.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/allwinner,sun60i-a733-emmc.yaml diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun60i-a733-emmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun60i-a733-emmc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..07dc6759b937c8998c4ca72cae027f9444a0793c --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun60i-a733-emmc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/allwinner,sun60i-a733-emmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A733 eMMC controller + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +description: + The SMHC3 controller has a different DMA descriptor format from SMHC0-2, + with 12-bit buffer lengths and high address bits in the descriptor control + word. It is not compatible with the earlier Allwinner MMC controllers. + +allOf: + - $ref: mmc-controller.yaml + +properties: + compatible: + const: allwinner,sun60i-a733-emmc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: AHB interface clock + - description: Module clock + - description: Storage MBUS clock + - description: MSI-Lite1 interface clock + + clock-names: + items: + - const: ahb + - const: mmc + - const: mbus + - const: msi + + resets: + maxItems: 1 + + reset-names: + const: ahb + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + mmc@4023000 { + compatible = "allwinner,sun60i-a733-emmc"; + reg = <0x04023000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>, + <&ccu CLK_MBUS_STORE>, <&ccu CLK_BUS_MSI_LITE1>; + clock-names = "ahb", "mmc", "mbus", "msi"; + resets = <&ccu RST_BUS_MMC3>; + reset-names = "ahb"; + }; base-commit: d89e1d186ec9271bf78e62771779e9fc03bf0fc3 prerequisite-patch-id: 0df2ae41836b86fd868dfa01ddfde57f888f761a prerequisite-patch-id: 88f3a431e7c551a9fa732f062188f10fdd362eeb prerequisite-patch-id: 3e88bc873c909059d1199f82cda4013765e7a5e5 prerequisite-patch-id: 0dbc27cd7417352319a0705a051dff35085e8922 prerequisite-patch-id: 0ed6b92774b5b794761c7ce34db653a5435dc833 prerequisite-patch-id: 27ed3814dbd0c7ad830532ff125625917c873b4b prerequisite-patch-id: 74d03898c5ce14763f4e89fb73e021de59f0fb9f prerequisite-patch-id: 9225cb094cf6cbb338b14ac63711d68bed12d24d prerequisite-patch-id: 568dae1c91a0d7318d6eb14a18054343b84b603a prerequisite-patch-id: ff3806332e741f0e2c8dac1c11f4c71449c16c8c prerequisite-patch-id: 39461e0543aefb5c40184664625cbab19ac8408a prerequisite-patch-id: 6fc03bfbd343042dd3b660938fcc09c5e7d48314 -- 2.53.0