[PATCH] pinctrl: realtek: Write the encoded slew rate value

["Baek Kyu, Kim" <pocj8ur4in@gmail.com>]

rtd_pconf_parse_conf() maps slew-rate arguments 1, 10, 20 and 30 to the
two-bit field values 0, 1, 2 and 3. However, it shifts the original
argument into the register value instead of using the computed encoding.
After masking, these arguments write 1, 2, 0 and 2 respectively. In
particular, the distinct 10 and 30 settings write the same field value.

Use set_val when constructing the register value so that both individual
pin and group configuration apply the existing conversion. Leave argument
validation, field offsets, masks and regmap error handling unchanged.

Fixes: dcc9334435b0 ("pinctrl: realtek: add support for slew rate, input voltage and high VIL")
Signed-off-by: Baek Kyu, Kim <pocj8ur4in@gmail.com>
---
An arm64 QEMU kernel exercised the RTD1625 MAIN2 pin and group
state-selection paths using the real pinctrl callbacks and a synthetic
regmap backend. A slew-rate request of 10 wrote field value 2 before
the change and 1 after it, while adjacent bits were preserved. No
board device tree, physical MMIO or signal timing was tested.

 drivers/pinctrl/realtek/pinctrl-rtd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c
index 60222339726b4..656c281c557ac 100644
--- a/drivers/pinctrl/realtek/pinctrl-rtd.c
+++ b/drivers/pinctrl/realtek/pinctrl-rtd.c
@@ -438,7 +438,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data,
 		sr_off = config_desc->base_bit + config_desc->slew_rate_offset;
 		reg_off = config_desc->reg_offset;
 		mask = 0x3 << sr_off;
-		val = arg << sr_off;
+		val = set_val << sr_off;
 		break;
 
 	case PIN_CONFIG_INPUT_VOLTAGE_UV:
-- 
2.55.0