From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com,
jroedel@suse.de, zong.li@sifive.com, andrew.jones@linux.dev,
anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca,
kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com,
vasant.hegde@amd.com, joerg.roedel@amd.com,
tanchi25@mails.ucas.ac.cn, gong.shuai@sanechips.com.cn
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
Nutty Liu <nutty.liu@hotmail.com>
Subject: [PATCH v6 09/10] iommu/riscv: Add dirty tracking support for second-stage domains
Date: Sat, 31 Oct 2026 16:30:13 +0800 [thread overview]
Message-ID: <20261031083014.15040-10-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20261031083014.15040-1-fangyu.yu@linux.alibaba.com>
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Add hardware dirty tracking support for second-stage (iohgatp) domains
used in KVM VFIO device pass-through.
The RISC-V IOMMU can automatically set the dirty bit in PTEs on write
access when DC.tc.GADE is set and the hardware has AMO_HWAD capability.
Wire this up to the iommufd dirty tracking interface:
- riscv_iommu_set_dirty_tracking(): Always enabled dirty tracking for
second-stage domain.
- riscv_iommu_dirty_ops: Exposes set_dirty_tracking and the generic
page-table read_and_clear_dirty via IOMMU_PT_DIRTY_OPS(riscv_64).
- domain_alloc_paging_flags: Assigns dirty_ops to second-stage domains
when AMO_HWAD is advertised in hardware capabilities.
- riscv_iommu_capable: Reports IOMMU_CAP_DIRTY_TRACKING when
AMO_HWAD is present.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
---
drivers/iommu/riscv/iommu.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index fc7a80393833..9f572baeca74 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -1377,6 +1377,21 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,
return 0;
}
+static int riscv_iommu_set_dirty_tracking(struct iommu_domain *iommu_domain,
+ bool enable)
+{
+ /*
+ * Always enabled and the dirty bitmap is cleared prior to
+ * set_dirty_tracking().
+ */
+ return 0;
+}
+
+static const struct iommu_dirty_ops riscv_iommu_dirty_ops = {
+ IOMMU_PT_DIRTY_OPS(riscv_64),
+ .set_dirty_tracking = riscv_iommu_set_dirty_tracking,
+};
+
static const struct iommu_domain_ops riscv_iommu_paging_domain_ops = {
IOMMU_PT_DOMAIN_OPS(riscv_64),
.attach_dev = riscv_iommu_attach_paging_domain,
@@ -1439,6 +1454,9 @@ static int riscv_iommu_init_domain_s2(struct device *dev,
if (domain->gscid < 0)
return -ENOMEM;
+ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD)
+ domain->domain.dirty_ops = &riscv_iommu_dirty_ops;
+
return 0;
}
@@ -1559,9 +1577,13 @@ static struct iommu_group *riscv_iommu_device_group(struct device *dev)
static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap)
{
+ struct riscv_iommu_device *iommu = dev_to_iommu(dev);
+
switch (cap) {
case IOMMU_CAP_CACHE_COHERENCY:
return dev_is_dma_coherent(dev);
+ case IOMMU_CAP_DIRTY_TRACKING:
+ return !!(iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD);
default:
return false;
}
--
2.50.1
next prev parent reply other threads:[~2026-10-31 8:30 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-31 8:30 [PATCH v6 00/10] iommu/riscv: Add hardware dirty tracking " fangyu.yu
2026-10-31 8:30 ` [PATCH v6 01/10] iommu/generic_pt: Fix the RISC-V supported feature mask fangyu.yu
2026-10-31 8:30 ` [PATCH v6 02/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-10-31 8:30 ` [PATCH v6 03/10] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-10-31 8:30 ` [PATCH v6 04/10] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-10-31 8:30 ` [PATCH v6 05/10] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-10-31 8:30 ` [PATCH v6 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-10-31 8:30 ` [PATCH v6 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-10-31 8:30 ` [PATCH v6 08/10] iommu/riscv: Pre-enable GADE for second-stage domains fangyu.yu
2026-10-31 8:30 ` fangyu.yu [this message]
2026-10-31 8:30 ` [PATCH v6 10/10] iommu/riscv: Add IOTINVAL.GVMA invalidations fangyu.yu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261031083014.15040-10-fangyu.yu@linux.alibaba.com \
--to=fangyu.yu@linux.alibaba.com \
--cc=alex@ghiti.fr \
--cc=andrew.jones@linux.dev \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atish.patra@linux.dev \
--cc=baolu.lu@linux.intel.com \
--cc=gong.shuai@sanechips.com.cn \
--cc=guoren@kernel.org \
--cc=iommu@lists.linux.dev \
--cc=jgg@nvidia.com \
--cc=jgg@ziepe.ca \
--cc=joerg.roedel@amd.com \
--cc=joro@8bytes.org \
--cc=jroedel@suse.de \
--cc=kevin.tian@intel.com \
--cc=kvm-riscv@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=nutty.liu@hotmail.com \
--cc=palmer@dabbelt.com \
--cc=pjw@kernel.org \
--cc=robin.murphy@arm.com \
--cc=skhawaja@google.com \
--cc=tanchi25@mails.ucas.ac.cn \
--cc=tomasz.jeznach@linux.dev \
--cc=vasant.hegde@amd.com \
--cc=will@kernel.org \
--cc=zong.li@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®