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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a42a5fb97sm27341792eec.23.2026.11.01.01.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Nov 2026 01:04:56 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mohd Ayaan Anwar , Zhangfei Gao , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support Date: Sun, 1 Nov 2026 16:04:11 +0800 Message-ID: <20261101080413.1428016-2-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261101080413.1428016-1-shengchao.guo@oss.qualcomm.com> References: <20261101080413.1428016-1-shengchao.guo@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: sbv7wmwKD1BuOeXyJR70liuj-K6aJtgL X-Authority-Analysis: v=2.4 cv=Z4F5j3RA c=1 sm=1 tr=0 ts=6ae6f2aa cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=IYcdIu6zbkOkbaNsF2sA:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAxMDAzMiBTYWx0ZWRfX7zTefKy585bk v7G61ghj4HJ9lxy82O2tkI6RgdcIPXAY48XbyLSpsVBIPDrBSPvN1SBwhXpuEXpjhJMQe1E+CCx 640CQy2nq6SJ4Q7LI3N8xstTbWd4udo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAxMDAzMiBTYWx0ZWRfX8+NMjhb4+J7h 6ZK8w9iFWIg/fmsdq8eHEkTX72sVlp2Z8wP5sNPY8W7px+wZ+BS43E9iTnettfO+qYh0U7oCPhe JctSCRneyhwq/1FFDjP/QEyspgfugB0yBOQAekJIO+u61ts32vWVJrosM0sqT5PE0Gr5m/4cQel U9mDlpP2lbUd4Lmmru7SgmZLd98NhONn+W97rWeA6a71z/unnjpg/Ot5n8maRNNi0k4RsHy5x7R wLMtbSbLO8okltD767V+q6O4nQNlrQG5QMQGZp+uOvE4r0zrugaugYsRshKM994x6eapvy0w4aZ 3v3+V4b/IFyiF+NOZs+ENM4F9ZiQifVrj9Mhnvi520IbLviKlyYqZhJojwntNPg8PZovalcvBqC klZKuYF4BH5Ml4jJ7KpTBlelapwEtlf1UfD3H+0MLoxtDJzDXTAFOlDo6nSwTYGgiHdUFis1gHH bKS4Uc2lCadMcoqJiuw== X-Proofpoint-ORIG-GUID: sbv7wmwKD1BuOeXyJR70liuj-K6aJtgL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-01_02,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611010032 From: Mohd Ayaan Anwar Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams and DMA queues. Signed-off-by: Mohd Ayaan Anwar Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 124 +++++++++ arch/arm64/boot/dts/qcom/nord.dtsi | 282 ++++++++++++++++++++ 2 files changed, 406 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi index 6dc4c871f41e..72094c84e346 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -42,6 +42,60 @@ &crypto { status = "okay"; }; +ðernet0 { + clocks = <&segcc SE_GCC_EMAC0_AXI_CLK>, + <&segcc SE_GCC_EMAC0_CNOC_APB_CLK>, + <&segcc SE_GCC_EMAC0_PTP_CLK>, + <&segcc SE_GCC_EMAC0_PHY_AUX_CLK>, + <&segcc SE_GCC_EEE_EMAC0_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "phyaux", + "eee"; + + resets = <&segcc SE_GCC_EMAC0_BCR>; + + power-domains = <&segcc SE_GCC_EMAC0_GDSC>; + + interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PS_ETH_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_EMAC_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-mac", + "mac-mem"; + + phys = <&serdes0>; + phy-names = "serdes"; +}; + +ðernet1 { + clocks = <&segcc SE_GCC_EMAC1_AXI_CLK>, + <&segcc SE_GCC_EMAC1_CNOC_APB_CLK>, + <&segcc SE_GCC_EMAC1_PTP_CLK>, + <&segcc SE_GCC_EMAC1_PHY_AUX_CLK>, + <&segcc SE_GCC_EEE_EMAC1_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "phyaux", + "eee"; + + resets = <&segcc SE_GCC_EMAC1_BCR>; + + power-domains = <&segcc SE_GCC_EMAC1_GDSC>; + + interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PS_ETH_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-mac", + "mac-mem"; + + phys = <&serdes1>; + phy-names = "serdes"; +}; + &i2c0 { clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; @@ -857,6 +911,30 @@ hpass_ag_noc: interconnect@5fc0000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + serdes0: phy@88f8000 { + compatible = "qcom,nord-dwmac-sgmii-phy"; + reg = <0x0 0x088f8000 0x0 0x4000>; + + clocks = <&tcsrcc TCSR_UX_SGMII_0_CLKREF_EN>; + clock-names = "sgmi_ref"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + serdes1: phy@88fc000 { + compatible = "qcom,nord-dwmac-sgmii-phy"; + reg = <0x0 0x088fc000 0x0 0x4000>; + + clocks = <&tcsrcc TCSR_UX_SGMII_1_CLKREF_EN>; + clock-names = "sgmi_ref"; + + #phy-cells = <0>; + + status = "disabled"; + }; + negcc: clock-controller@8900000 { compatible = "qcom,nord-negcc"; reg = <0x0 0x08900000 0x0 0xf4200>; @@ -1106,6 +1184,38 @@ nsp_data_noc_3: interconnect@1fe00000 { }; &tlmm { + ethernet0_default: ethernet0-default-state { + mdc-pins { + pins = "gpio47"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio48"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ethernet1_default: ethernet1-default-state { + mdc-pins { + pins = "gpio49"; + function = "emac1_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio50"; + function = "emac1_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + qup_i2c0_default: qup-i2c0-default-state { pins = "gpio111", "gpio112"; function = "qup0_se0"; @@ -1989,3 +2099,17 @@ opp-403000000 { }; }; }; + +&xpcs0 { + clocks = <&segcc SE_GCC_EMAC0_CNOC_APB_CLK>; + clock-names = "csr"; + + power-domains = <&segcc SE_GCC_EMAC0_GDSC>; +}; + +&xpcs1 { + clocks = <&segcc SE_GCC_EMAC1_CNOC_APB_CLK>; + clock-names = "csr"; + + power-domains = <&segcc SE_GCC_EMAC1_GDSC>; +}; diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi index dfbbaf94a7ae..586fedd2580d 100644 --- a/arch/arm64/boot/dts/qcom/nord.dtsi +++ b/arch/arm64/boot/dts/qcom/nord.dtsi @@ -1593,6 +1593,288 @@ rng: rng@10c3000 { reg = <0x0 0x010c3000 0x0 0x1000>; }; + ethernet0: ethernet@1a00000 { + compatible = "qcom,nord-ethqos"; + + reg = <0x0 0x01a00000 0x0 0x14000>, + <0x0 0x01a7f000 0x0 0x1000>; + reg-names = "stmmaceth", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", + "eth_lpi"; + + iommus = <&apps_smmu_2 0x1201 0x2>, + <&apps_smmu_2 0x1202 0x0>, + <&apps_smmu_2 0x1203 0x2>, + <&apps_smmu_2 0x1204 0x0>, + <&apps_smmu_2 0x1205 0x2>, + <&apps_smmu_2 0x1206 0x0>, + <&apps_smmu_2 0x1207 0x2>, + <&apps_smmu_2 0x1208 0x0>, + <&apps_smmu_2 0x1209 0x0>, + <&apps_smmu_2 0x120a 0x0>; + + pcs-handle = <&xpcs0>; + + dma-coherent; + + rx-fifo-depth = <98304>; + tx-fifo-depth = <98304>; + + snps,tso; + snps,pbl = <16>; + snps,axi-config = <&emac0_axi_setup>; + snps,mtl-rx-config = <&emac0_mtl_rx>; + snps,mtl-tx-config = <&emac0_mtl_tx>; + + status = "disabled"; + + emac0_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <16>; + snps,rd_osr_lmt = <16>; + snps,blen = <0 0 0 0 16 0 0>; + }; + + emac0_mtl_rx: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + emac0_mtl_tx: tx-queues-config { + snps,tx-queues-to-use = <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + xpcs0: xpcs@1a14000 { + compatible = "qcom,nord-dw-xpcs"; + + reg = <0x0 0x01a14000 0x0 0x5100>; + reg-names = "direct"; + reg-io-width = <4>; + + status = "disabled"; + }; + + ethernet1: ethernet@1a80000 { + compatible = "qcom,nord-ethqos"; + + reg = <0x0 0x01a80000 0x0 0x14000>, + <0x0 0x01aff000 0x0 0x1000>; + reg-names = "stmmaceth", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", + "eth_lpi"; + + iommus = <&apps_smmu_2 0x11c1 0x8>, + <&apps_smmu_2 0x11c2 0x1>, + <&apps_smmu_2 0x11c3 0x1>, + <&apps_smmu_2 0x11c4 0x3>, + <&apps_smmu_2 0x11c5 0x3>, + <&apps_smmu_2 0x11c6 0x3>, + <&apps_smmu_2 0x11c7 0x3>, + <&apps_smmu_2 0x11c8 0x2>, + <&apps_smmu_2 0x11c9 0x8>, + <&apps_smmu_2 0x11ca 0x2>; + + pcs-handle = <&xpcs1>; + + dma-coherent; + + rx-fifo-depth = <98304>; + tx-fifo-depth = <98304>; + + snps,tso; + snps,pbl = <16>; + snps,axi-config = <&emac1_axi_setup>; + snps,mtl-rx-config = <&emac1_mtl_rx>; + snps,mtl-tx-config = <&emac1_mtl_tx>; + + status = "disabled"; + + emac1_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <16>; + snps,rd_osr_lmt = <16>; + snps,blen = <0 0 0 0 16 0 0>; + }; + + emac1_mtl_rx: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + emac1_mtl_tx: tx-queues-config { + snps,tx-queues-to-use = <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + xpcs1: xpcs@1a94000 { + compatible = "qcom,nord-dw-xpcs"; + + reg = <0x0 0x01a94000 0x0 0x5100>; + reg-names = "direct"; + reg-io-width = <4>; + + status = "disabled"; + }; + ufs_mem_hc: ufshc@1d44000 { compatible = "qcom,nord-ufshc", "qcom,ufshc", -- 2.43.0