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([218.239.109.48]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a426681aesm35700172eec.1.2026.11.01.08.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Nov 2026 08:44:50 -0800 (PST) From: =?UTF-8?q?GIBEOM=20LEE=20=28=EC=9D=B4=EA=B8=B0=EB=B2=94=29?= To: Mark Brown , Liam Girdwood Cc: AngeloGioacchino Del Regno , Matthias Brugger , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, =?UTF-8?q?GIBEOM=20LEE=20=28=EC=9D=B4=EA=B8=B0=EB=B2=94=29?= Subject: [PATCH 1/2] regulator: mt6363: Use 8-bit regmap values Date: Mon, 2 Nov 2026 01:44:03 +0900 Message-ID: <20261101164405.1743177-2-rtx4060@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261101164405.1743177-1-rtx4060@gmail.com> References: <20261101164405.1743177-1-rtx4060@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The registers of the MT6363 are 8 bits wide, but the regmap has 16-bit values. On SPMI that makes every access two bytes long: a read also returns the next register in the upper byte, and a write also writes the next register, with 0 or with what a read-modify-write found there. The next register is rarely related to the one the driver means, so this goes wrong in several places: - mt6363_vreg_disable_setclr() writes the mask to the CLR register and 0 to the one after it. For VS2 and VBUCK1-7 that is the enable register of VS1, VS3 and VSRAM_{DIGRF,MDFE,MODEM}, so disabling any of them disables those five as well. For those five it is the low power register of VS2 and VBUCK1-7. - mt6363_regulator_set_load() zeroes the register after OP_CFG and the one after the third OP_EN register. - A read-modify-write of the low power register of a buck writes back to its SET register what it read from it. If SET reads like the register itself, that sets again the bit that was just cleared. - TOP_TRAP is read together with MISC_TOP_INT_CON0, so the VEMC voltage callbacks fail with -EINVAL once a MISC interrupt is enabled. - regmap_bulk_write() takes a number of registers. The sizeof() of the u16 keys of TMA and BUCK_TOP asks for two 16-bit registers, so it reads past the key on the stack and writes that to the two registers after the key. MediaTek's regulator driver uses the regmap of their MFD driver, which has 8-bit values (mt6363-regulator.c and mtk-spmi-pmic.c in the OnePlus MT6897 kernel, OnePlusOSS android_kernel_modules_and_devicetree_oneplus_mt6897, branch oneplus/mt6897_b_16.0.0_oneplus_pad). With 8-bit values one access is one register, and the sizeof() of the keys is the right number of registers. Fixes: 3c36965df808 ("regulator: Add support for MediaTek MT6363 SPMI PMIC Regulators") Assisted-by: Claude:claude-opus-5-5 Signed-off-by: GIBEOM LEE (이기범) --- drivers/regulator/mt6363-regulator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/regulator/mt6363-regulator.c b/drivers/regulator/mt6363-regulator.c index aa6a8eb..cc2e841 100644 --- a/drivers/regulator/mt6363-regulator.c +++ b/drivers/regulator/mt6363-regulator.c @@ -811,7 +811,7 @@ static struct regmap *mt6363_spmi_register_regmap(struct device *dev) { struct regmap_config mt6363_regmap_config = { .reg_bits = 16, - .val_bits = 16, + .val_bits = 8, .max_register = 0x1f90, .fast_io = true, };