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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3aebaac28c9sm2045136a91.15.2026.11.01.09.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Nov 2026 09:46:52 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Anna Maniscalco , Rob Clark , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/4] drm/msm: Rework IFPC disable Date: Sun, 1 Nov 2026 09:46:25 -0800 Message-ID: <20261101174631.23637-2-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261101174631.23637-1-robin.clark@oss.qualcomm.com> References: <20261101174631.23637-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: uAfwvKIBxLgc-GBSWKtX6P_jPrHfikA_ X-Authority-Analysis: v=2.4 cv=QuvLTlyd c=1 sm=1 tr=0 ts=6ae77b0e cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=sgg8FroAFpLa0IqUokEA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: uAfwvKIBxLgc-GBSWKtX6P_jPrHfikA_ X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAxMDA3MCBTYWx0ZWRfX0Gj7oy5Gz/qj GiE7tGJ7vAEjs2XBlzLmFZDaF7EM8UGsLTKwfJvRFono+dfXnzEf3vBYTL2zLZX3qpSbykJ9VWY 0Dr/BG609thh3p1eCv/u6FXpg1MBaRA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAxMDA3MCBTYWx0ZWRfX+N8S0lwOY6oQ N797fNW0Nrz/dYfUvP44z6FDhzGhZE2T6fuq0lmUqAf0JSNxP14J9SdenYUsfwxhBLOG1XevsIY N5uvzVnuKu24IcFlWnisXMzOfh6biNpfARhz7sRR3xq/zEJTKSkDCHUDdwn1iXLM2/3q/nOQRIs B9fK3BZzR94cSUvHISw3ykYtRCJFr0upDQCfZmlA9xz4lgnQMIy51ybBRbl+5dGINEwZEWW/koj 4eQ14Bpw8qQ1xq4Q1x0KIKS4jNbZx5t6ql7lCNWr872wjmpKYe7ZkBHyj/qVyFX+xekB/jIEDXm jMYdWJzt30qESVsucU4EPUlTpJW44i4nksmWbSE5oG9hmLwB1m1lodQP0tsst/YAeZU2Tuo1rxm OBkdc15KeK3EnR6ghveOE1L1oUtRmX9A3e/XE7VwhUri52nKq3ro30Z6mz3jt+EP/DFTGKDFbn1 xiPPslpcZr5qzeCHYEw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-01_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 malwarescore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611010070 Previously this was coupled to SYSPROF level, which made sense at the time. But there are other places that we need to inhibit IFPC. So decouple it from the sysprof refcount. Now it has it's own refcount, so multiple threads can vote to inhibit IFPC safely. The renamed gpu->ifpc_update() simply applies the new state by setting or clearing an OOB request. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 ++++-------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.c | 1 + drivers/gpu/drm/msm/msm_gpu.h | 26 ++++++++++++++++++++++---- drivers/gpu/drm/msm/msm_perfcntr.c | 6 ++---- drivers/gpu/drm/msm/msm_submitqueue.c | 10 ++++++---- 7 files changed, 40 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 662f09bec9d5..d1fe6c40da83 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2128,12 +2128,12 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, return irq; } -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on) +void a6xx_gmu_ifpc_update(struct msm_gpu *gpu) { - bool sysprof = msm_gpu_sysprof_no_ifpc(gpu) || force_on; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + bool force_on = refcount_read(&gpu->ifpc_disable) > 1; /* Nothing to do if GPU is suspended. We will handle this during GMU resume */ if (!pm_runtime_get_if_active(&gpu->pdev->dev)) @@ -2145,9 +2145,9 @@ void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on) * 'Perfcounter select' register values are lost during IFPC collapse. To avoid that, * use the currently unused perfcounter oob vote to block IFPC when sysprof is active */ - if (sysprof && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + if (force_on && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); - else if (!sysprof && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + else if (!force_on && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); mutex_unlock(&gmu->lock); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 74064eba98c7..3de6892d1b9c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1565,11 +1565,7 @@ static int hw_init(struct msm_gpu *gpu) a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); } - if (!ret && msm_gpu_sysprof_no_ifpc(gpu)) { - ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); - if (!ret) - set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); - } + a6xx_gmu_ifpc_update(gpu); return ret; } @@ -2851,7 +2847,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a6xx_progress, - .sysprof_setup = a6xx_gmu_sysprof_setup, + .ifpc_update = a6xx_gmu_ifpc_update, .perfcntr_configure = a6xx_perfcntr_configure, }, .init = a6xx_gpu_init, @@ -2922,7 +2918,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a6xx_progress, - .sysprof_setup = a6xx_gmu_sysprof_setup, + .ifpc_update = a6xx_gmu_ifpc_update, .perfcntr_configure = a6xx_perfcntr_configure, }, .init = a6xx_gpu_init, @@ -2960,7 +2956,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a8xx_progress, - .sysprof_setup = a6xx_gmu_sysprof_setup, + .ifpc_update = a6xx_gmu_ifpc_update, .perfcntr_configure = a6xx_perfcntr_configure, .perfcntr_flush = a8xx_perfcntr_flush, }, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 36717b511316..077b5cb60896 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -298,7 +298,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on); +void a6xx_gmu_ifpc_update(struct msm_gpu *gpu); void a6xx_preempt_init(struct msm_gpu *gpu); void a6xx_preempt_hw_init(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index fb07803f5aba..37f9e93daa43 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -1012,6 +1012,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, gpu->nr_rings = nr_rings; refcount_set(&gpu->sysprof_active, 1); + refcount_set(&gpu->ifpc_disable, 1); mutex_init(&gpu->perfcntr_lock); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index d27d54bdb7a7..0334a0f604ac 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -93,7 +93,7 @@ struct msm_gpu_funcs { * for cmdstream that is buffered in this FIFO upstream of the CP fw. */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); - void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on); + void (*ifpc_update)(struct msm_gpu *gpu); /* Configure perfcntr SELect regs: */ void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring, @@ -186,6 +186,14 @@ struct msm_gpu { */ refcount_t sysprof_active; + /** + * ifpc_disable: + * + * Count of votes to disable IFPC (1-based, values above 1 mean IFPC + * is disabled). + */ + refcount_t ifpc_disable; + /** * lock: * @@ -375,10 +383,20 @@ msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) (gpu->perfcntrs && READ_ONCE(gpu->perfcntrs->stream)); } -static inline bool -msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu) +static inline void +msm_gpu_disable_ifpc_get(struct msm_gpu *gpu) +{ + refcount_inc(&gpu->ifpc_disable); + if (gpu->funcs->ifpc_update) + gpu->funcs->ifpc_update(gpu); +} + +static inline void +msm_gpu_disable_ifpc_put(struct msm_gpu *gpu) { - return refcount_read(&gpu->sysprof_active) > 1; + refcount_dec(&gpu->ifpc_disable); + if (gpu->funcs->ifpc_update) + gpu->funcs->ifpc_update(gpu); } /* diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_perfcntr.c index ce65b1160955..867dd476ed88 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.c +++ b/drivers/gpu/drm/msm/msm_perfcntr.c @@ -259,8 +259,7 @@ sample_worker(struct kthread_work *work) } /* Inhibit IFPC while accessing registers: */ - if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu, true); + msm_gpu_disable_ifpc_get(gpu); if (gpu->funcs->perfcntr_flush) gpu->funcs->perfcntr_flush(gpu); @@ -297,8 +296,7 @@ sample_worker(struct kthread_work *work) } /* Re-enable IFPC: */ - if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu, false); + msm_gpu_disable_ifpc_put(gpu); smp_store_release(&stream->fifo.head, head); wake_up_all(&stream->poll_wq); diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index d307cdd17d90..8434a09319bc 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -24,7 +24,10 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy pm_runtime_get_sync(&gpu->pdev->dev); fallthrough; case 1: + /* Disable zapping perfcntrs on context switch: */ refcount_inc(&gpu->sysprof_active); + /* Disable IFPC: */ + msm_gpu_disable_ifpc_get(gpu); fallthrough; case 0: break; @@ -36,16 +39,15 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy pm_runtime_put_autosuspend(&gpu->pdev->dev); fallthrough; case 1: + /* Drop our vote for inhibiting IFPC: */ + msm_gpu_disable_ifpc_put(gpu); + /* Drop our vote for disabling perfcntr zapping: */ refcount_dec(&gpu->sysprof_active); fallthrough; case 0: break; } - /* Some gpu families require additional setup for sysprof */ - if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu, false); - ctx->sysprof = sysprof; return 0; -- 2.56.0