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Sun, 01 Nov 2026 10:57:48 -0800 (PST) Received: from hp ([71.12.40.102]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8b2b716d420sm40869397b3.33.2026.11.01.10.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Nov 2026 10:57:48 -0800 (PST) From: Tim Michals To: Jassi Brar , Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-sunxi@lists.linux.dev, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tim Michals Subject: [PATCH v3 1/7] dt-bindings: mailbox: Add Allwinner A523 message box Date: Sun, 1 Nov 2026 12:57:29 -0600 Message-ID: <20261101185735.762559-2-tcmichals@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261101185735.762559-1-tcmichals@gmail.com> References: <20261101185735.762559-1-tcmichals@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Allwinner A523, A527 and T527 (sun55i) message box connects the Cortex-A55 host with the HiFi4 DSP, the CPUS power management core and the XuanTie E906 RISC-V core. Each processor has its own register bank. A sender writes a message into the receiving processor's bank, and a channel has an 8-entry FIFO in each direction. The host bank has 12 channels, four for each remote processor. The binding lists all four banks, since the host writes to and reads the FIFO status of the remote banks, and lists the bank interrupts in the same order: the host bank read interrupt and the write interrupts of the three remote banks, which every A523 has. Each bank has its own bus clock and reset, and an unclocked bank drops writes, so all four are described. The optional allwinner,tx-done-irq property selects TX completion by the receiver bank's write interrupt instead of polling. Signed-off-by: Tim Michals --- Changes in v3: - One compatible, allwinner,sun55i-a523-msgbox: the A523, A527 and T527 are the same die; the A733 entry is dropped - reg, clocks and resets list all four banks in a fixed order, with clock-names and reset-names: every bank has its own bus clock and reset - interrupts and interrupt-names are a fixed list (arm, dsp, cpus, rv), all four required: every A523 has the four lines, and allwinner,tx-done-irq only selects how TX done is detected. This answers the v1 question of how an interrupt can be optional; no free-form text (Krzysztof) - Remote bank interrupts in the example corrected to SPI 181/174/205 (T527 manual, Table 2-15; checked on the board) - reg: the DSP and CPUS bank addresses were swapped in v2 (0x07120000 is the DSP bank, 0x07094000 the CPUS bank) - Add allwinner,tx-done-irq - Description rewritten to describe the hardware; "schema" dropped from the subject (Krzysztof) - Samuel Holland dropped from the maintainers --- .../mailbox/allwinner,sun55i-a523-msgbox.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml b/Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml new file mode 100644 index 000000000000..47b6fe304dbc --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/allwinner,sun55i-a523-msgbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A523 Message Box + +maintainers: + - Tim Michals + +description: + The message box on the Allwinner A523, A527 and T527 (sun55i) SoCs links + four processors - the Cortex-A55 cluster, the HiFi4 DSP, the CPUS power + management core and the XuanTie E906 RISC-V core. Each processor has its + own register bank holding 8-entry receive FIFOs for messages from the + other three, and a sender writes into the receiver's bank. The host side + therefore uses all four banks and exposes 12 channels, 4 per remote + processor. Each bank has its own bus clock and reset, and an unclocked + bank drops writes, so the host needs all four. A bank's read interrupt + goes to the processor that owns it; its write interrupt, raised while the + FIFO has room, goes to the sender on a separate line. + +properties: + compatible: + const: allwinner,sun55i-a523-msgbox + + reg: + items: + - description: Cortex-A55 host bank + - description: HiFi4 DSP bank + - description: CPUS bank + - description: XuanTie RISC-V bank + + reg-names: + items: + - const: arm + - const: dsp + - const: cpus + - const: rv + + clocks: + items: + - description: Cortex-A55 host bank bus clock + - description: HiFi4 DSP bank bus clock + - description: CPUS bank bus clock + - description: XuanTie RISC-V bank bus clock + + clock-names: + items: + - const: arm + - const: dsp + - const: cpus + - const: rv + + resets: + items: + - description: Cortex-A55 host bank reset + - description: HiFi4 DSP bank reset + - description: CPUS bank reset + - description: XuanTie RISC-V bank reset + + reset-names: + items: + - const: arm + - const: dsp + - const: cpus + - const: rv + + interrupts: + items: + - description: Cortex-A55 bank read interrupt, messages for the host + - description: HiFi4 DSP bank write interrupt for the host + - description: CPUS bank write interrupt for the host + - description: XuanTie RISC-V bank write interrupt for the host + + interrupt-names: + items: + - const: arm + - const: dsp + - const: cpus + - const: rv + + allwinner,tx-done-irq: + type: boolean + description: + Signal TX done with the write interrupt of the receiver's bank instead + of polling. A message is done once the receiver's FIFO has room for the + next one either way; the write interrupt is raised while the FIFO has + room. Without this property a full FIFO is polled. Received messages + use the host bank read interrupt either way. + + '#mbox-cells': + const: 1 + description: + Host channel number. Channels 0-3 reach the CPUS, 4-7 the DSP and + 8-11 the RISC-V core. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - resets + - reset-names + - interrupts + - interrupt-names + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + mailbox@3003000 { + compatible = "allwinner,sun55i-a523-msgbox"; + reg = <0x03003000 0x1000>, + <0x07120000 0x1000>, + <0x07094000 0x1000>, + <0x07136000 0x1000>; + reg-names = "arm", "dsp", "cpus", "rv"; + clocks = <&ccu CLK_BUS_MSGBOX>, + <&mcu_ccu CLK_BUS_MCU_DSP_MSGBOX>, + <&r_ccu CLK_BUS_R_MSGBOX>, + <&mcu_ccu CLK_BUS_MCU_RISCV_MSGBOX>; + clock-names = "arm", "dsp", "cpus", "rv"; + resets = <&ccu RST_BUS_MSGBOX>, + <&mcu_ccu RST_BUS_MCU_DSP_MSGBOX>, + <&r_ccu RST_BUS_R_MSGBOX>, + <&mcu_ccu RST_BUS_MCU_RISCV_MSGBOX>; + reset-names = "arm", "dsp", "cpus", "rv"; + interrupts = , + , + , + ; + interrupt-names = "arm", "dsp", "cpus", "rv"; + #mbox-cells = <1>; + }; -- 2.53.0