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Mon, 2 Nov 2026 11:05:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793617548; bh=dOrw03ZY4M0Y/JC7nnm0OdrkCVNUcDRGbuVdDy6WXrg=; h=From:Subject:Date:To:Cc:Reply-To; b=YvD/ucDpSBv3rK8itVesUFA6gAWbCc0AUT6TbbSKgOZhUB5ZBSi9Q6fU5nwmP0ahI k3WbDqtZsx+Ihag3GvALimV+jtWw9tzCwnKDjQdnkG2YUPbO0g0r+bhAs5qEWZqrI5 wfIi9clTPXNc7mU9/d6kkE82SUStr42Ynx/nTeNYRF1YUIvGq8s8XuKZasgzB4ESit VbbGjhqZEaYUDsRc6Zkq7D4PYRj8CDywmmZ92JHHDHf2+/H+htGykar5UqSuQpMqx3 VLwpEGi0C5xMr+BTlrpZ4lxcfMPG8Cd0x5raI3xYLGRV7MY6jDD60rW4qsTzYVv/xh NW31Z4IRVT5CQ== Received: from nexus.subspace.kernel.org (localhost [IPv6:::1]) by lkml.kernel.org (Postfix) with ESMTP id 1D3E3464AD; Mon, 2 Nov 2026 11:05:47 +0000 (UTC) From: Junyi Zhao via B4 Relay Subject: [PATCH v2 0/2] Add Amlogic A9 I3C support Date: Mon, 02 Nov 2026 19:05:38 +0800 Message-Id: <20261102-a9_i3c-v2-0-0c474bfccffa@amlogic.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAIJu6GoC/zWNyw6DIBQFf8XcdWkAH5Gu/I/GNBRQb1OlAUvaG P69YONykjlzNvDGofFwKTZwJqBHuyTgpwLUJJfRENSJgVPeMMookeKGpSJC17yqNRWVaiHJL2c G/Oyha/9n/74/jFrzOhsT+tW67/4UWPaOqDiigRFKSi50y4RuOBs6OT/tiOqs7Ax9jPEHtvKD/ rAAAAA= X-Change-ID: 20261010-a9_i3c-9d5245d094c8 To: Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Miquel Raynal , Kees Cook , "Gustavo A. R. Silva" Cc: linux-i3c@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, imx@lists.linux.dev, linux-hardening@vger.kernel.org, xianwei.zhao@amlogic.com, Kelvin.Zhang@amlogic.com, Junyi Zhao X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793617545; l=1695; i=junyi.zhao@amlogic.com; s=20260924; h=from:subject:message-id; bh=UJx6v15t+vGPfwRUpHt2I4ZrP80lRsdJGExEg/joTkI=; b=18IKIcD3tbqV1AO5x5M/aDMWsCEGnolOANX6OlHDU5VZtiKG9Yc8hSPlxSfaAGD1RSWjtCX/g RqH0pwQyVEiC/nAKTPWnya0TuURq6v+ASS1FxJPezuDRnUqKoehW52b X-Developer-Key: i=junyi.zhao@amlogic.com; a=ed25519; pk=hiL5PjGIksGFiWvEx9J3MhQqU/ro6vNbj72NIw4bbvA= X-Endpoint-Received: by B4 Relay for junyi.zhao@amlogic.com/20260924 with auth_id=1054 X-Original-From: Junyi Zhao Reply-To: junyi.zhao@amlogic.com Amlogic A9 SoCs integrate the Silvaco I3C IP, but their peripheral clock setup differs from the original implementation: the EE-domain controller (amlogic,a9-i3c) takes two clocks, "pclk" and "fast_clk", while the AO-domain controller (amlogic,a9-ao-i3c) exposes only "pclk" and derives its bus clock from an internal divider inside the controller's own register region. This series consists of: - Add a vendor_init callback for the clock setup and a vendor_quirks field for AO-specific behaviour to the Silvaco I3C master driver, and enable the existing Silvaco workaround quirks for both Amlogic variants. - Add the Amlogic compatibles and per-variant clock constraints to the silvaco,i3c-master binding schema. Verified on Amlogic A9 (BY401) with both EE and AO controller instances. dt_binding_check and dtbs_check pass with this series. Signed-off-by: Junyi Zhao --- Changes in v2: - No need rework the Silvaco I3C driver. - Based on vanilla driver, adapt A9 SoCS through callback and quirks to handle the variant. - Link to v1: https://patch.msgid.link/20261019-a9_i3c-v1-0-329d819d621f@amlogic.com --- Junyi Zhao (2): i3c: master: svc: Add amlogic a9 support dt-bindings: i3c: silvaco,i3c-master: Add Amlogic A9 support .../bindings/i3c/silvaco,i3c-master.yaml | 24 ++- drivers/i3c/master/svc-i3c-master.c | 214 ++++++++++++++++++++- 2 files changed, 231 insertions(+), 7 deletions(-) --- base-commit: aac26bee2287c88af5be5a5ff96d783b19a28790 change-id: 20261010-a9_i3c-9d5245d094c8 Best regards, -- Junyi Zhao