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Mon, 02 Nov 2026 19:02:10 -0800 (PST) Received: from localhost ([2600:1702:7a90:6f9f:8bc4:8aec:108d:7a04]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-67baf2b96a6sm6475377d50.12.2026.11.02.19.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 19:02:09 -0800 (PST) From: Matt Turner Date: Mon, 02 Nov 2026 22:02:01 -0500 Subject: [PATCH v4 6/7] alpha/perf: attach ProfileMe status as PERF_SAMPLE_RAW data X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261102-alpha-profileme-v4-6-61e00f5e1da8@gmail.com> References: <20261102-alpha-profileme-v4-0-61e00f5e1da8@gmail.com> In-Reply-To: <20261102-alpha-profileme-v4-0-61e00f5e1da8@gmail.com> To: Richard Henderson , Magnus Lindholm , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark Cc: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Matt Turner X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4962; i=mattst88@gmail.com; h=from:subject:message-id; bh=5NFJ1lFerIJO/yu7TqCglFw+N0D49Hyz85jS7IyduTU=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLJe+i1513BT6sHlNV6a4isuVnFfSXu3doKZlVVpi4tc6 zVnW9WLHR9ZGMS4GGaKKbLErVdkmdW2Y6nPaelfMHNYmUCGSIs0MAABCwNfbmJeqZGOkZ6ptqGe IZChYxQPkdNj0MgsLi5NLdJNKyhyyMsvSSzJzM8r1ssvSM0rSC/QS8tMK8nIyC8qTgUaoZeXWmL q6uhmZGhgYuloYeZk4Whq4uzsZOjk5ujo7OpkZGluYuBs6WjiamnOwMUpAHPN+XyG/04eVWd/rv dliHvttvlLpnD+cZvg/OXzWFbOtz9W5CIv957hn53S+qnTy1+sq3iu69SmWhRYtdsl87Pwu44/M s0zPeUU2AE= X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A A ProfileMe sample's PC alone does not say what happened to the profiled instruction. I_STAT and PCTR_CTL do: whether it trapped and why, was mispredicted, stalled, or was killed on a wrong path, and what PCTR1 counted during the window. With PERF_SAMPLE_RAW, attach PMPC, I_STAT and PCTR_CTL to each ProfileMe sample in a versioned struct alpha_profileme_sample. PMPC is included because a PALmode PMPC is not the sample's IP. Killed instructions can be told apart by PM_KILLED_BM and VAL. The 64-bit fields are packed after the 32-bit version, since the payload follows the 32-bit raw size in the sample record: they are then 8-byte aligned in the record, which needs no padding. Signed-off-by: Matt Turner Reviewed-by: Magnus Lindholm Tested-by: Magnus Lindholm --- arch/alpha/include/asm/perf_event.h | 2 ++ arch/alpha/include/uapi/asm/perf_event.h | 31 +++++++++++++++++++++++++++++++ arch/alpha/kernel/perf_event.c | 22 +++++++++++++++++++--- 3 files changed, 52 insertions(+), 3 deletions(-) diff --git a/arch/alpha/include/asm/perf_event.h b/arch/alpha/include/asm/perf_event.h index 72536566014a..f498c1d47c07 100644 --- a/arch/alpha/include/asm/perf_event.h +++ b/arch/alpha/include/asm/perf_event.h @@ -1,6 +1,8 @@ #ifndef __ASM_ALPHA_PERF_EVENT_H #define __ASM_ALPHA_PERF_EVENT_H +#include + /* * Software events have no trap frame, so perf_fetch_caller_regs() fills * in a zeroed pt_regs. A zero ps already means kernel mode; only pc is diff --git a/arch/alpha/include/uapi/asm/perf_event.h b/arch/alpha/include/uapi/asm/perf_event.h new file mode 100644 index 000000000000..aa0eff5a917c --- /dev/null +++ b/arch/alpha/include/uapi/asm/perf_event.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _UAPI_ASM_ALPHA_PERF_EVENT_H +#define _UAPI_ASM_ALPHA_PERF_EVENT_H + +#include + +/* + * PERF_SAMPLE_RAW payload of a ProfileMe sample from the cpu PMU. + * + * pmpc, i_stat and pctr_ctl are the values of the PMPC, I_STAT and + * PCTR_CTL registers when the ProfileMe window closed. i_stat holds only + * bits 40:30 and pctr_ctl only bits 47:0. See the EV67/EV68 Hardware + * Reference Manuals for the field layout. + * + * In the sample record the payload follows the 32-bit PERF_SAMPLE_RAW + * size, so it starts 4 bytes past an 8-byte boundary. The 64-bit fields + * are packed after the 32-bit version so that they are 8-byte aligned in + * the record and no padding follows the payload. + * + * Fields may be added to the end in later versions. + */ +#define ALPHA_PROFILEME_SAMPLE_VERSION 1 + +struct alpha_profileme_sample { + __u32 version; + __u64 pmpc __attribute__((packed)); + __u64 i_stat __attribute__((packed)); + __u64 pctr_ctl __attribute__((packed)); +}; + +#endif /* _UAPI_ASM_ALPHA_PERF_EVENT_H */ diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index 29577a493e55..862824ed6a68 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -988,11 +988,14 @@ static void alpha_perf_event_profileme(struct perf_event *event, struct hw_perf_event *hwc, struct pt_regs *regs) { + struct alpha_profileme_sample pm; + struct perf_raw_record raw; struct perf_sample_data data; struct pt_regs *pm_regs; bool pc_only = false; - unsigned long i_stat, pmpc, ovr, pc, saved_pc, saved_ps; + unsigned long pctr_ctl, i_stat, pmpc, ovr, pc, saved_pc, saved_ps; + pctr_ctl = wrperfmon(PERFMON_CMD_READ, 0); i_stat = wrperfmon(PERFMON_CMD_I_STAT, 0); pmpc = wrperfmon(PERFMON_CMD_PMPC, 0); @@ -1029,8 +1032,8 @@ static void alpha_perf_event_profileme(struct perf_event *event, * happens for ITB miss, Istream access violation and interrupt * redirects, and for instructions inside PALcode. Keep the * interrupted PC, which for redirects is the instruction that - * trapped. Do the same for a user PMPC in a kernel thread, which has - * no user frame. + * trapped, and report the real PMPC in the raw data. Do the same + * for a user PMPC in a kernel thread, which has no user frame. */ pm_regs = regs; pc = pmpc & EV67_PMPC_PC_MASK; @@ -1065,6 +1068,19 @@ static void alpha_perf_event_profileme(struct perf_event *event, else if (in_entry_save_code(pc) && is_user_task(current)) alpha_profileme_set_regs_user(event, &data); + pm.version = ALPHA_PROFILEME_SAMPLE_VERSION; + pm.pmpc = pmpc; + pm.i_stat = i_stat; + /* PALcode sign-extends bit 47 of PCTR_CTL. */ + pm.pctr_ctl = pctr_ctl & GENMASK(47, 0); + raw = (struct perf_raw_record) { + .frag = { + .size = sizeof(pm), + .data = &pm, + }, + }; + perf_sample_save_raw_data(&data, event, &raw); + if (!alpha_perf_event_set_period(event, hwc, 0)) return; -- 2.55.0