From: Krzysztof Kozlowski <krzk@kernel.org>
To: Cunhao Lu <1579567540@qq.com>
Cc: Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Philipp Zabel <p.zabel@pengutronix.de>,
Elaine Zhang <zhangqing@rock-chips.com>,
Richard Cochran <richardcochran@gmail.com>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org
Subject: Re: [PATCH v5 1/4] dt-bindings: clock: rockchip: Add RK3572 CRU
Date: Mon, 2 Nov 2026 09:02:59 +0100 [thread overview]
Message-ID: <20261102-casual-free-starling-fd87a5@quoll> (raw)
In-Reply-To: <20261030-add-board-ok3572-c-clk-v5-1-9a43403cb149@qq.com>
On Fri, Oct 30, 2026 at 05:43:57PM +0800, Cunhao Lu wrote:
> From: Elaine Zhang <zhangqing@rock-chips.com>
>
> The RK3572 CRU uses the PMU0 GRF for the AUPLL reference mux.
> Describe the controller and define its clock and reset IDs.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> [adapted to mainline rockchip clock and reset handling (xin24m input,
> don't introduce CLK_NR_CLKS)]
> Signed-off-by: Cunhao Lu <1579567540@qq.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-11-02 8:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-30 9:43 [PATCH v5 0/4] clk: rockchip: Add RK3572 clock and reset support Cunhao Lu via B4 Relay
2026-10-30 9:43 ` [PATCH v5 1/4] dt-bindings: clock: rockchip: Add RK3572 CRU Cunhao Lu via B4 Relay
2026-11-02 8:02 ` Krzysztof Kozlowski [this message]
2026-10-30 9:43 ` [PATCH v5 2/4] clk: rockchip: Add internal support for 24-bit fractional dividers Cunhao Lu via B4 Relay
2026-11-13 21:25 ` Heiko Stuebner
2026-10-30 9:43 ` [PATCH v5 3/4] clk: rockchip: Add composite clock macro with mux table Cunhao Lu via B4 Relay
2026-10-30 9:44 ` [PATCH v5 4/4] clk: rockchip: Add RK3572 clock and reset support Cunhao Lu via B4 Relay
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