From: Conor Dooley <conor@kernel.org>
To: Han Gao <rabenda.cn@gmail.com>
Cc: gaohan@iscas.ac.cn, Drew Fustini <fustini@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
Rob Herring <robh@kernel.org>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,
Radu Rendec <radu@rendec.net>,
Zhiguo Zhu <zhiguo.zhu@linux.alibaba.com>,
devicetree@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Bartosz Golaszewski <brgl@kernel.org>,
linux-gpio@vger.kernel.org,
Daniel Lezcano <daniel.lezcano@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Linus Walleij <linusw@kernel.org>,
linux-kernel@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Thomas Gleixner <tglx@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Paul Walmsley <pjw@kernel.org>
Subject: Re: [PATCH 17/18] riscv: defconfig: enable A210 support
Date: Mon, 2 Nov 2026 19:11:49 +0000 [thread overview]
Message-ID: <20261102-conductor-expanse-db86270fc1a6@spud> (raw)
In-Reply-To: <20261102142300.3784622-1-rabenda.cn@gmail.com>
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On Mon, Nov 02, 2026 at 10:22:53PM +0800, Han Gao wrote:
> On Thu, 22 Oct 2026 19:50:51 +0100 Conor Dooley <conor@kernel.org> wrote:
>
> > On Thu, Oct 22, 2026 at 03:53:37AM +0800, Han Gao via B4 Relay wrote:
> > > From: Han Gao <gaohan@iscas.ac.cn>
> > >
> > > Enable A210 platform drivers and reserve ten 8250 UART ports.
> > >
> > > Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> > > ---
> > > arch/riscv/configs/defconfig | 4 ++++
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > > index 04ae305d5511..b9b3bca12089 100644
> > > --- a/arch/riscv/configs/defconfig
> > > +++ b/arch/riscv/configs/defconfig
> > > @@ -33,6 +33,7 @@ CONFIG_SOC_STARFIVE=y
> > > CONFIG_ARCH_SUNXI=y
> > > CONFIG_ARCH_TENSTORRENT=y
> > > CONFIG_ARCH_THEAD=y
> > > +CONFIG_ARCH_ZHIHE=y
> > > CONFIG_ARCH_ULTRARISC=y
> > > CONFIG_ARCH_VIRT=y
> > > CONFIG_ARCH_CANAAN=y
> > > @@ -149,6 +150,8 @@ CONFIG_KEYBOARD_GPIO=y
> > > CONFIG_KEYBOARD_SUN4I_LRADC=m
> > > CONFIG_SERIAL_8250=y
> > > CONFIG_SERIAL_8250_CONSOLE=y
> > > +CONFIG_SERIAL_8250_NR_UARTS=10
> > > +CONFIG_SERIAL_8250_RUNTIME_UARTS=10
> >
> > Why are these options needed?
>
> The A210 has 10 UARTs and the TH1520 has 6. With the default of 4,
> UARTs beyond the 4th don't get a fixed ttyS index and end up in
> whatever slot is free. Raising both to 10 keeps the index stable.
Put this in the commit message please.
>
> >
> > > CONFIG_SERIAL_8250_DW=y
> > > CONFIG_SERIAL_OF_PLATFORM=y
> > > CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
> > > @@ -167,6 +170,7 @@ CONFIG_SPI_PL022=m
> > > CONFIG_SPI_SIFIVE=y
> > > CONFIG_SPI_SUN6I=y
> > > # CONFIG_PTP_1588_CLOCK is not set
> > > +CONFIG_PINCTRL_A210=y
> > > CONFIG_PINCTRL_TH1520=y
> > > CONFIG_PINCTRL_SOPHGO_CV1800B=y
> > > CONFIG_PINCTRL_SOPHGO_CV1812H=y
> > >
> > > --
> > > 2.55.0
> > >
> > >
> >
>
> Sent using hkml (https://github.com/sjp38/hackermail)
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next prev parent reply other threads:[~2026-11-02 19:11 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-21 19:53 [PATCH 00/18] riscv: add initial support for Zhihe A210 and Melon Pi Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 01/18] dt-bindings: vendor-prefixes: add Zhihe Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 02/18] riscv: add Zhihe A210 support Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 03/18] dt-bindings: clock: add Zhihe A210 clock controllers Han Gao via B4 Relay
2026-10-22 18:52 ` Conor Dooley
2026-10-21 19:53 ` [PATCH 04/18] dt-bindings: clock: add Zhihe A210 AON clock controller Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 05/18] clk: zhihe: add A210 support Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 06/18] dt-bindings: reset: add Zhihe A210 reset controllers Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 07/18] reset: zhihe: add A210 support Han Gao via B4 Relay
2026-10-22 9:22 ` Philipp Zabel
2026-10-21 19:53 ` [PATCH 08/18] dt-bindings: pinctrl: add Zhihe A210 pin controller Han Gao via B4 Relay
2026-10-22 19:01 ` Conor Dooley
2026-10-21 19:53 ` [PATCH 09/18] pinctrl: zhihe: add A210 support Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 10/18] dt-bindings: interrupt-controller: add Zhihe A210 PLIC Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 11/18] dt-bindings: riscv: add Melon Pi V1 and V2 Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 12/18] dt-bindings: timer: add Zhihe A210 CLINT Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 13/18] riscv: dts: zhihe: add A210 core support Han Gao via B4 Relay
2026-10-22 18:48 ` Conor Dooley
2026-11-02 14:30 ` Han Gao
2026-10-21 19:53 ` [PATCH 14/18] riscv: dts: zhihe: add A210 UARTs Han Gao via B4 Relay
2026-10-22 9:22 ` Philipp Zabel
2026-11-02 14:24 ` Han Gao
2026-10-21 19:53 ` [PATCH 15/18] riscv: dts: zhihe: add A210 module memory Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 16/18] riscv: dts: zhihe: add Melon Pi V1 and V2 Han Gao via B4 Relay
2026-10-21 19:53 ` [PATCH 17/18] riscv: defconfig: enable A210 support Han Gao via B4 Relay
2026-10-22 18:50 ` Conor Dooley
2026-11-02 14:22 ` Han Gao
2026-11-02 19:11 ` Conor Dooley [this message]
2026-10-21 19:53 ` [PATCH 18/18] MAINTAINERS: add Zhihe A210 Han Gao via B4 Relay
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