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Each child node can carry its own interrupts, iommus, and power-domains properties. The implementation is split into three functions: - fsl_edma_child_to_chan_id(): derives the channel index from the child MMIO address relative to the parent base. - fsl_edma_configure_chan_from_dt(): called before setup_irq() to populate per-channel txirq from child interrupt properties. fsl_edma3_irq_init() is updated to skip platform_get_irq() for channels that already have an IRQ assigned from their child node. - fsl_edma_configure_chan_iommu(): called after dmaenginem_async_device_register() to configure per-channel IOMMU by calling of_dma_configure() on each dma_chan_dev and setting chan_dma_dev so dmaengine_get_dma_device() returns the per-channel device. Existing DTS without child nodes continues to work unchanged. Signed-off-by: Peng Fan --- drivers/dma/fsl-edma-common.c | 10 +-- drivers/dma/fsl-edma-main.c | 152 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 152 insertions(+), 10 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 513b0f4e5be21..62cd60179bc6f 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -310,10 +310,10 @@ int fsl_edma_resume(struct dma_chan *chan) static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan) { + struct device *dev = dmaengine_get_dma_device(&fsl_chan->vchan.chan); + if (fsl_chan->dma_dir != DMA_NONE) - dma_unmap_resource(fsl_chan->vchan.chan.device->dev, - fsl_chan->dma_dev_addr, - fsl_chan->dma_dev_size, + dma_unmap_resource(dev, fsl_chan->dma_dev_addr, fsl_chan->dma_dev_size, fsl_chan->dma_dir, 0); fsl_chan->dma_dir = DMA_NONE; } @@ -321,7 +321,7 @@ static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan) static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan, enum dma_transfer_direction dir) { - struct device *dev = fsl_chan->vchan.chan.device->dev; + struct device *dev = dmaengine_get_dma_device(&fsl_chan->vchan.chan); enum dma_data_direction dma_dir; phys_addr_t addr = 0; u32 size = 0; @@ -1090,7 +1090,7 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan) if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) clk_prepare_enable(fsl_chan->clk); - fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, + fsl_chan->tcd_pool = dma_pool_create("tcd_pool", dmaengine_get_dma_device(chan), fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ? sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd), 32, 0); diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 30d548a723462..795744e67837d 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -16,7 +16,10 @@ #include #include #include +#include +#include #include +#include #include #include #include @@ -400,12 +403,13 @@ static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engi if (fsl_edma->chan_masked & BIT(i)) continue; - /* request channel irq */ - fsl_chan->txirq = platform_get_irq(pdev, i); - if (fsl_chan->txirq < 0) - return -EINVAL; + if (fsl_chan->txirq <= 0) { + fsl_chan->txirq = platform_get_irq(pdev, i); + if (fsl_chan->txirq < 0) + return fsl_chan->txirq; - fsl_chan->irq_handler = fsl_edma3_tx_handler; + fsl_chan->irq_handler = fsl_edma3_tx_handler; + } if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_ERRIRQ_SHARE)) { fsl_chan->errirq = fsl_chan->txirq; @@ -703,6 +707,136 @@ static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_eng return -EINVAL; } +static int fsl_edma_child_to_chan_id(struct platform_device *pdev, + struct fsl_edma_engine *fsl_edma, + struct device_node *child, + struct resource *parent_res) +{ + const struct fsl_edma_drvdata *drvdata = fsl_edma->drvdata; + struct resource child_res; + u32 ch_id; + int ret; + + ret = of_address_to_resource(child, 0, &child_res); + if (ret) + return ret; + + if (child_res.start < parent_res->start + drvdata->chreg_off) + return -EINVAL; + + ch_id = (child_res.start - parent_res->start - drvdata->chreg_off) + / drvdata->chreg_space_sz; + + if (ch_id >= fsl_edma->n_chans) + return -EINVAL; + + return ch_id; +} + +static int fsl_edma_configure_chan_from_dt(struct platform_device *pdev, + struct fsl_edma_engine *fsl_edma) +{ + struct device_node *np = pdev->dev.of_node; + struct resource parent_res; + struct device_node *child; + int ret; + + ret = of_address_to_resource(np, 0, &parent_res); + if (ret) + return ret; + + for_each_available_child_of_node(np, child) { + struct fsl_edma_chan *fsl_chan; + int ch_id, irq; + + ch_id = fsl_edma_child_to_chan_id(pdev, fsl_edma, child, + &parent_res); + if (ch_id < 0) { + dev_err(&pdev->dev, "invalid channel in %pOFn\n", child); + of_node_put(child); + return -EINVAL; + } + + if (fsl_edma->chan_masked & BIT(ch_id)) + continue; + + fsl_chan = &fsl_edma->chans[ch_id]; + + irq = of_irq_get(child, 0); + if (irq == -EPROBE_DEFER) { + of_node_put(child); + return -EPROBE_DEFER; + } + if (irq > 0) { + fsl_chan->txirq = irq; + fsl_chan->irq_handler = fsl_edma3_tx_handler; + } + } + + return 0; +} + +static int fsl_edma_configure_chan_iommu(struct platform_device *pdev, + struct fsl_edma_engine *fsl_edma) +{ + struct device_node *np = pdev->dev.of_node; + struct resource parent_res; + struct device_node *child; + struct dma_chan *chan; + int ret; + + ret = of_address_to_resource(np, 0, &parent_res); + if (ret) + return ret; + + for_each_available_child_of_node(np, child) { + struct fsl_edma_chan *fsl_chan; + int ch_id; + + if (!of_property_present(child, "iommus")) + continue; + + ch_id = fsl_edma_child_to_chan_id(pdev, fsl_edma, child, + &parent_res); + if (ch_id < 0) + continue; + + if (fsl_edma->chan_masked & BIT(ch_id)) + continue; + + fsl_chan = &fsl_edma->chans[ch_id]; + + list_for_each_entry(chan, &fsl_edma->dma_dev.channels, + device_node) { + struct device *chdev; + + if (to_fsl_edma_chan(chan) != fsl_chan) + continue; + + chdev = dmaengine_chan_dev(chan); + if (fsl_edma->drvdata->flags & FSL_EDMA_DRV_TCD64) + dma_coerce_mask_and_coherent(chdev, + DMA_BIT_MASK(64)); + else + dma_coerce_mask_and_coherent(chdev, + DMA_BIT_MASK(32)); + ret = of_dma_configure(chdev, child, true); + if (ret) { + dev_err(&pdev->dev, + "IOMMU config failed for channel %d: %d\n", + ch_id, ret); + of_node_put(child); + return ret; + } + + chan->chan_dev->chan_dma_dev = true; + break; + } + } + + return 0; +} + static int fsl_edma_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -836,6 +970,10 @@ static int fsl_edma_probe(struct platform_device *pdev) clk_disable_unprepare(fsl_chan->clk); } + ret = fsl_edma_configure_chan_from_dt(pdev, fsl_edma); + if (ret) + return ret; + ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); if (ret) return ret; @@ -898,6 +1036,10 @@ static int fsl_edma_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, ret, "Can't register Freescale eDMA engine.\n"); + ret = fsl_edma_configure_chan_iommu(pdev, fsl_edma); + if (ret) + return ret; + ret = devm_of_dma_controller_register(&pdev->dev, np, drvdata->dmamuxs ? fsl_edma_xlate : fsl_edma3_xlate, fsl_edma); -- 2.34.1