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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3aebaac28c9sm5053234a91.15.2026.11.02.01.47.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 01:47:33 -0800 (PST) From: Jie Gan Date: Mon, 02 Nov 2026 17:46:31 +0800 Subject: [PATCH v21 3/8] coresight: tmc: add a function to switch the ETR to a free etr_buf X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261102-enable-byte-cntr-for-ctcu-v21-3-231e069b7853@oss.qualcomm.com> References: <20261102-enable-byte-cntr-for-ctcu-v21-0-231e069b7853@oss.qualcomm.com> In-Reply-To: <20261102-enable-byte-cntr-for-ctcu-v21-0-231e069b7853@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jie Gan , Bjorn Andersson , Konrad Dybcio , Yuanfang Zhang , Mao Jinlong , Abel Vesa Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793612829; l=4491; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=e7qSmNkg1bJ9CuA5XfZ/wTAAZZTOW6tXZW1EGCi+WMY=; b=xcyDWk4tPPulZu+qTEV4TTf9k8ChipkC2MqSxxOK3fOjIHDtEQPzWqfqUCK3APffkY8SUjvOH AOPzBqxBOi3De8xgqdjlgRhtZ5zsasb5Lkh/Lt8FJRXkGrBro9ZQdgJ X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Authority-Analysis: v=2.4 cv=TMDQ2Fla c=1 sm=1 tr=0 ts=6ae85c37 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=XrOnqjNa2oMXnLqE:21 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=TPt5YZYWydgKV8fuSqQA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: wlItFtYEDIeEhcV8Lxq4SXyPui6YyMVL X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAyMDAzOCBTYWx0ZWRfX3nfeRf1UCinp uZgRgSrtut+E0VvphsV4pb0IIAvRXMu03aaDSbooM7GELw1riUiz1OjPQCEc5p+IXu4i4F0tjp+ EckKYpcyXD07WMWnqFUyeq2V/l3rnyc= X-Proofpoint-ORIG-GUID: wlItFtYEDIeEhcV8Lxq4SXyPui6YyMVL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAyMDAzOCBTYWx0ZWRfX90FpjsMKS8R0 Kw7UXTu6a497uhkFr0VLos7a6CoDOlFVDlZc6mbCWwt2/lUCGuJfEBg86xg9itSVj6iDJ/Xe/7z QRjf2Y76UZZvlo/P19VzL+X42ZkimZ0B6ZDK2Hb/am4cb0aNo6iKydzApOK4zUx2PJYaj+2YcGn dY+Rjo1aNYMmX+FbBxB6+syN7I9kvArLQwTz12NPvZf+tjQ0aY5KfhXRCz0pL9/6KSYq3Wz3d3S h3FhjsyOcDJ5CmoMzSPqrqnNFefgNlReZysjkYpRsGR/piYtnEjb4vHfCDkG5xp2MweK1HC+Iad GH5apN7+ZPifSS/PzTRc8tWXJ3572y9fH+Iye2lqi/6961guHxCMBtu/ydPXEf0d8RRXIXDfu/a eU+aPSRmRPastKWTN1mzcRjZvEszQqHkS4v5qP61tXxuTnT/RtGNNXB+BmMOcJMe5Rdz0Wn9E5a DxChtX9Eb0gTfHTslRg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-02_03,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611020038 Add tmc_etr_switch_buf_node() to switch the ETR to a free etr_buf of the etr_buf_list without disabling the sink. It returns the node of the switched out etr_buf, so its synced data can be read while the ETR keeps tracing into the new one. Stopping the ETR, swapping the etr_buf and restarting the ETR have to be done in one critical section. Otherwise tmc_disable_etr_sink() can run in between and leave drvdata->etr_buf out of sync with the hardware. Provide the sequence as a TMC helper, so callers don't need to know about the locking of the ETR state. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 65 +++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 4 ++ 2 files changed, 69 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index eee98a9269df..2de31d73a4b4 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1224,6 +1224,71 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) } +static void tmc_etr_reset_sysfs_buf(struct tmc_drvdata *drvdata) +{ + u32 sts; + + CS_UNLOCK(drvdata->base); + tmc_write_rrp(drvdata, drvdata->sysfs_buf->hwaddr); + tmc_write_rwp(drvdata, drvdata->sysfs_buf->hwaddr); + sts = readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL; + writel_relaxed(sts, drvdata->base + TMC_STS); + CS_LOCK(drvdata->base); +} + +/** + * tmc_etr_switch_buf_node - switch the ETR to a free buffer of the etr_buf_list. + * @drvdata: drvdata of the TMC device. + * + * Stop the ETR, hand over the current buffer for reading, switch to a free + * buffer and restart the ETR. All of this is done with @drvdata->spinlock held, + * so it can't race with the sink disable path. + * + * Return: the node of the switched out buffer, or NULL if the sink isn't in + * sysfs mode or there is no free buffer. The ETR is left untouched in both + * cases. + */ +struct etr_buf_node *tmc_etr_switch_buf_node(struct tmc_drvdata *drvdata) +{ + struct etr_buf_node *nd, *curr_node = NULL, *picked_node = NULL; + unsigned long flags; + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (coresight_get_mode(drvdata->csdev) != CS_MODE_SYSFS) + goto out; + + list_for_each_entry(nd, &drvdata->etr_buf_list, link) { + if (nd->sysfs_buf == drvdata->sysfs_buf) + curr_node = nd; + else if (!picked_node && nd->is_free) + picked_node = nd; + } + + if (!curr_node || !picked_node) { + curr_node = NULL; + goto out; + } + + __tmc_etr_disable_hw(drvdata); + + /* The switched out buffer is free again once it has been read */ + curr_node->is_free = true; + curr_node->pos = 0; + curr_node->reading = true; + picked_node->is_free = false; + drvdata->sysfs_buf = picked_node->sysfs_buf; + drvdata->etr_buf = picked_node->sysfs_buf; + + tmc_etr_reset_sysfs_buf(drvdata); + if (__tmc_etr_enable_hw(drvdata)) + dev_err(&drvdata->csdev->dev, "Failed to restart the ETR\n"); +out: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return curr_node; +} +EXPORT_SYMBOL_GPL(tmc_etr_switch_buf_node); + void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) { __tmc_etr_disable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 7c604b9f92e5..30b15c38b080 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -212,12 +212,15 @@ struct tmc_resrv_buf { * struct etr_buf_node - node of the etr_buf_list * @sysfs_buf: Allocated sysfs_buf. * @is_free: Indicates whether the buffer is free to choose. + * @reading: Indicates the buffer attached to the node is being read by + * the user. * @pos: Offset to the start of the buffer. * @link: list_head of the node. */ struct etr_buf_node { struct etr_buf *sysfs_buf; bool is_free; + bool reading; loff_t pos; struct list_head link; }; @@ -465,5 +468,6 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, extern const struct attribute_group coresight_etr_group; void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata); int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes); +struct etr_buf_node *tmc_etr_switch_buf_node(struct tmc_drvdata *drvdata); #endif -- 2.34.1