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The command queue carries commands from the driver to GSP-RM, and the message queue carries messages from GSP-RM to the driver. Each ring buffer has a write pointer and a read pointer. Msgq v0, which the r570 firmware uses, keeps both pointers of each ring buffer in that ring buffer's header, in shared memory. Msgq v2, which the r000 firmware uses, keeps the four pointers, two per ring buffer, in four BAR0 registers instead: NV_PGSP_QUEUE_HEAD command queue write pointer NV_PGSP_QUEUE_TAIL command queue read pointer NV_PGSP_MSGQ_HEAD message queue write pointer NV_PGSP_MSGQ_TAIL message queue read pointer The GSP numbers its queues 0 through 7, and each numbered queue is one such pair of ring buffers with its own four pointer registers. Nova-core uses queue 0 only. A write to NV_PGSP_QUEUE_HEAD also interrupts the GSP. Msgq v0 uses that write as the doorbell, so nova-core already declares NV_PGSP_QUEUE_HEAD. Declare the other three, NV_PGSP_QUEUE_TAIL, NV_PGSP_MSGQ_HEAD and NV_PGSP_MSGQ_TAIL. No functional change intended. [ acourbot: declare the registers as arrays of 8 with a stride of 8. ] [ acourbot: use "val" for the field name of NV_PGSP_MSGQ as per OpenRM. ] Assisted-by: LLM Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gsp/cmdq.rs | 6 +++++- drivers/gpu/nova-core/gsp/regs.rs | 22 +++++++++++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs index 936406004a57..07b21a6f4504 100644 --- a/drivers/gpu/nova-core/gsp/cmdq.rs +++ b/drivers/gpu/nova-core/gsp/cmdq.rs @@ -15,6 +15,7 @@ io::{ io_project, poll::read_poll_timeout, + register::Array, Io, // }, new_mutex, @@ -496,7 +497,10 @@ fn calculate_checksum>(it: T) -> u32 { /// Notifies the GSP that we have updated the command queue pointers. fn notify_gsp(bar: Bar0<'_>) { - bar.write_reg(regs::NV_PGSP_QUEUE_HEAD::zeroed().with_address(0u32)); + bar.write( + Array::at(0), + regs::NV_PGSP_QUEUE_HEAD::zeroed().with_address(0u32), + ); } /// Logs and consumes every message the GSP has already posted, and returns without waiting for diff --git a/drivers/gpu/nova-core/gsp/regs.rs b/drivers/gpu/nova-core/gsp/regs.rs index 3c410d65e8e4..e3fbbf364b7b 100644 --- a/drivers/gpu/nova-core/gsp/regs.rs +++ b/drivers/gpu/nova-core/gsp/regs.rs @@ -9,12 +9,32 @@ // PGSP +// The GSP has eight numbered queues, each with its own four msgq pointer registers interleaved +// at a stride of 8 bytes. nova-core uses queue 0 only. + register! { base: NovaRegisters; - pub(super) NV_PGSP_QUEUE_HEAD(u32) @ 0x00110c00 { + /// Write pointer of the CPU-to-GSP command queue, which the driver advances. A write to this + /// register also interrupts the GSP, which makes it the doorbell. + pub(super) NV_PGSP_QUEUE_HEAD(u32)[8, stride = 8] @ 0x00110c00 { 31:0 address; } + + /// Read pointer of the CPU-to-GSP command queue, which the GSP advances. + pub(super) NV_PGSP_QUEUE_TAIL(u32)[8, stride = 8] @ 0x00110c04 { + 31:0 address; + } + + /// Write pointer of the GSP-to-CPU message queue, which the GSP advances. + pub(super) NV_PGSP_MSGQ_HEAD(u32)[8, stride = 8] @ 0x00110c80 { + 31:0 val; + } + + /// Read pointer of the GSP-to-CPU message queue, which the driver advances. + pub(super) NV_PGSP_MSGQ_TAIL(u32)[8, stride = 8] @ 0x00110c84 { + 31:0 val; + } } // PBUS -- 2.56.0